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1. 发明授权

US07544544B2 Low capacitance two-terminal barrier controlled TVS diodes 有权
标题翻译：低电容两端势垒控制TVS二极管
公开(公告)号：US07544544B2
公开(公告)日：2009-06-09
申请号：US11879424
申请日：2007-07-17
申请人： Adrian I. Cogan , Jin Qiu , Richard A. Blanchard
发明人： Adrian I. Cogan , Jin Qiu , Richard A. Blanchard
IPC分类号： H01L21/332
CPC分类号： H01L29/66136 , H01L27/0255 , H01L29/861
摘要： A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.
摘要翻译：两端势垒控制TVS二极管具有消耗区域阻挡阻挡多数载流子流过阴极区附近的沟道区域，该偏压电平低于施加在阳极电极和阴极电极之间的预定钳位电压的偏置电平，并且可布置使得阳极区域在半导体结构的导通期间通过将少数载流子注入沟道区域来提供导电性调制。在目前优选的形式中，多数载流子是电子，而少数载流子是空穴。描述制造方法。

2. 发明授权

US06373347B1 Power control circuits and methods 失效
标题翻译：功率控制电路和方法
公开(公告)号：US06373347B1
公开(公告)日：2002-04-16
申请号：US09369405
申请日：1999-08-05
申请人： Adrian I. Cogan
发明人： Adrian I. Cogan
IPC分类号： H01P122
CPC分类号： H02M5/06
摘要： The present invention provides simple, low cost power control circuits and methods for high frequency (e.g., RF) applications. According to one embodiment of the present invention, a high frequency circuit comprises a capacitor, a PTC element and a resistor. The PTC element is heated by a high frequency input signal and changes its resistance. The change in the resistance of the PTC element controls the output power of the circuit. In another embodiment of the present invention, the circuit comprises a high frequency circuit and a control circuit. The control circuit provides a DC current to the high frequency circuit to control the resistance of the PTC element, which in turn controls the output power of the high frequency circuit. In this embodiment, two separate paths are used: one for high frequency input signals and one for DC control current.
摘要翻译：本发明提供了用于高频（例如RF）应用的简单的低成本功率控制电路和方法。根据本发明的一个实施例，高频电路包括电容器，PTC元件和电阻器。 PTC元件由高频输入信号加热并改变其电阻。 PTC元件的电阻变化控制电路的输出功率。在本发明的另一实施例中，电路包括高频电路和控制电路。控制电路向高频电路提供直流电流，以控制PTC元件的电阻，继而控制高频电路的输出功率。在本实施例中，使用两个独立的路径：一个用于高频输入信号，一个用于DC控制电流。

3. 发明授权

US6153948A Electronic circuits with wide dynamic range of on/off delay time 失效
标题翻译：电子电路具有宽动态范围的开/关延迟时间
公开(公告)号：US6153948A
公开(公告)日：2000-11-28
申请号：US133334
申请日：1998-08-13
申请人： Adrian I. Cogan , Shukri J. Souri
发明人： Adrian I. Cogan , Shukri J. Souri
IPC分类号： H02H9/02 , H02H7/085 , H03K17/08 , H03K17/082 , H03K17/28 , H03K17/284 , H03K17/687 , H02J3/00
CPC分类号： H03K17/284 , H03K17/0822 , H02H7/0855 , H03K2017/0806 , Y10T307/773
摘要： The present invention provides an electronic circuit with adjustable delay time for turning on or off an application device or an electronic load. The electronic circuit according to the present invention comprises a switch element for controlling power supplied to a load; and an activation element, coupled to the switch element, for activating the switch element to control power supplied to the load. The activation element includes a sensor for sensing whether there is a change in condition and for delaying activation by the activation element of the switch element upon sensing a change in condition. In one embodiment of the invention, the sensor includes a positive temperature coefficient (PTC) element; the switch element includes a metal-oxide-semiconductor field effect transistor (MOSFET); and the activation element further includes a capacitor and a switch. A change in condition includes an overload and an increase in the ambient temperature.
摘要翻译：本发明提供一种具有可延迟时间的电子电路，用于打开或关闭应用装置或电子负载。根据本发明的电子电路包括用于控制供应给负载的电力的开关元件; 以及耦合到所述开关元件的激活元件，用于启动所述开关元件以控制提供给所述负载的功率。激活元件包括传感器，用于感测状态改变时是否存在状态变化和延迟启动元件的启动元件。在本发明的一个实施例中，传感器包括正温度系数（PTC）元件; 开关元件包括金属氧化物半导体场效应晶体管（MOSFET）; 并且所述激活元件还包括电容器和开关。条件的变化包括过载和环境温度的升高。

4. 发明授权

US4799100A Method and apparatus for increasing breakdown of a planar junction 失效
标题翻译：用于增加平面结的击穿的方法和装置
公开(公告)号：US4799100A
公开(公告)日：1989-01-17
申请号：US14961
申请日：1987-02-17
申请人： Richard A. Blanchard , Adrian I. Cogan
发明人： Richard A. Blanchard , Adrian I. Cogan
IPC分类号： H01L29/41 , H01L29/06 , H01L29/40 , H01L29/861 , H01L29/12
CPC分类号： H01L29/408 , H01L29/8611
摘要： In order to increase breakdown voltage of a planar junction of a semiconductor device, an oxide layer is provided on a portion of the surface of the semiconductor substrate and covers the junction at that surface, the oxide layer containing a charged ion region extending from the junction over a portion of the substrate, with the polarity of the ions being the same as the polarity of the substrate region over which the oxide layer extends.

5. 发明授权

US4791462A Dense vertical j-MOS transistor 失效
标题翻译：密集的垂直j-MOS晶体管
公开(公告)号：US4791462A
公开(公告)日：1988-12-13
申请号：US95481
申请日：1987-09-10
申请人： Richard A. Blanchard , Adrian I. Cogan
发明人： Richard A. Blanchard , Adrian I. Cogan
IPC分类号： H01L29/78 , H01L29/808
CPC分类号： H01L29/7832 , H01L29/8083
摘要： A j-MOS structure is disclosed which operates at high current densities and provides high current handling capability. A heavily doped N+ substrate, acting as a drain, has grown on it a lightly doped N- epitaxial layer. Within the epitaxial layer are multiple N+ buried regions, each within a corresponding P+ buried region, and bisecting each of the multiple N+ regions are vertical gates extending from the upper surface of the epitaxial layer down into the N+ substrate. These gates are insulated from the epitaxial layer and substrate via a thin gate oxide layer, but are electrically connected to the multiple N+ buried regions. Between each adjacent gate pair, N+ source regions are formed on the upper surface of the epitaxial layer. The gates are connected together via a conductive layer which also electrically shorts the gates to a poly-Si contact making contact with the N+ buried regions. The N+ source regions between the gates are also electrically connected together via the conductive layer, but are insulated from the gates and P+ and N+ buried regions.
摘要翻译：公开了以高电流密度工作并提供高电流处理能力的j-MOS结构。充当漏极的重掺杂N +衬底在其上生长了轻掺杂的N外延层。在外延层内的是多个N +掩埋区域，每一个在相应的P +掩埋区域内，并且将多个N +区域中的每一个平分，是从外延层的上表面向下延伸到N +衬底的垂直栅极。这些栅极经由薄栅氧化层与外延层和衬底绝缘，但是电连接到多个N +掩埋区。在每个相邻栅极对之间，在外延层的上表面上形成N +源极区。栅极通过导电层连接在一起，该导电层也将栅极电短路到与N +掩埋区接触的多晶硅接触。栅极之间的N +源极区域也经由导电层电连接在一起，但是与栅极和P +和N +掩埋区域绝缘。

6. 发明授权

US4786614A Method of fabricating a high voltage semiconductor device having a pair of V-shaped isolation grooves 失效
标题翻译：制造具有一对V形隔离槽的高电压半导体器件的方法
公开(公告)号：US4786614A
公开(公告)日：1988-11-22
申请号：US19085
申请日：1987-02-26
申请人： Adrian I. Cogan
发明人： Adrian I. Cogan
IPC分类号： H01L21/76 , H01L21/761 , H01L29/41 , H01L21/38
CPC分类号： H01L21/761 , H01L29/41
摘要： A method of fabricating a semiconductor device capable of handling high voltages includes forming a relatively thick epitaxial layer the top surface of which defines a plurality of generally V-shaped grooves, a pair of the grooves having formed therebetween active device regions, such pair of grooves acting as isolation regions including impurity regions extending on both sides of the groove through the epitaxial layer to a lower layer. A pair of grooves formed inward of the first-mentioned grooves contact active regions of the device into which the V-shaped portions extend, again with each such V-shaped portion having impurity regions extending on both sides thereof. The impurity regions associated with the V-shaped grooves are formed simultaneously with other active regions of the device.

7. 发明授权

US4716126A Fabrication of double diffused metal oxide semiconductor transistor 失效
标题翻译：双扩散金属氧化物半导体晶体管的制造
公开(公告)号：US4716126A
公开(公告)日：1987-12-29
申请号：US871006
申请日：1986-06-05
申请人： Adrian I. Cogan
发明人： Adrian I. Cogan
IPC分类号： H01L29/78 , H01L21/033 , H01L21/336 , H01L21/265 , H01L21/316
CPC分类号： H01L29/66712 , H01L21/033
摘要： In the fabrication process of a DMOS transistor, a window is formed between polysilicon gate regions. Nitrogen is then implanted in the window. A self-aligning oxide is deposited to cover the exposed side walls of the polysilicon gate regions. P-type impurities are implanted at the exposed surface of the window between the side walls. Using silicon nitride masking, an oxide plug is then grown in the window. N-type impurities are implanted in the window region to form a junction adjacent to the polysilicon gate regions. Metal contacts and a passivation layer are subsequently deposited by masking, and contact windows are formed to complete the transistor structure.

8. 发明授权

US4566172A Method of fabricating a static induction type recessed junction field effect transistor 失效
标题翻译：制造静态感应型凹结场效应晶体管的方法
公开(公告)号：US4566172A
公开(公告)日：1986-01-28
申请号：US583512
申请日：1984-02-24
申请人： Izak Bencuya , Adrian I. Cogan
发明人： Izak Bencuya , Adrian I. Cogan
IPC分类号： H01L21/335 , H01L29/10 , H01L21/425
CPC分类号： H01L29/66416 , H01L29/1066
摘要： Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. The depth of the grooves is increased by etching to remove most of the P-type zone underlying each groove while leaving laterally extending P-type portions. Oxygen is implanted to convert the remainder of the P-type zones underlying the end walls of the grooves to silicon dioxide. Metal layers are deposited in the bottoms of the grooves making contact with the P-type portions. The grooves are filled with filler material and materials are etched away to produce a flat, planar surface with low resistivity N-type silicon of the ridges exposed in the surface and with filler material in the grooves also exposed at the surface. A large area metal contact is applied which extends across the surface and makes ohmic contact to the low resistivity N-type silicon of all the ridges.
摘要翻译：结型场效应晶体管，特别是静态感应晶体管及其制造方法。在低电阻N型硅衬底上生长的高电阻率N型外延层的表面形成低电阻率N型层。低电阻率N型层的表面涂覆有氮化硅，部分氮化硅被去除并且蚀刻硅以形成具有插入的硅脊的平行凹槽。在凹槽中生长二氧化硅，从凹槽的端壁移除，并且在凹槽的端壁处形成P型区域。通过蚀刻来增加凹槽的深度以去除每个凹槽下面的大部分P型区域，同时留下横向延伸的P型部分。植入氧气以将槽的端壁下面的P型区域的其余部分转化为二氧化硅。金属层沉积在与P型部分接触的凹槽的底部。凹槽填充有填充材料，并且材料被蚀刻掉以产生平坦的平坦表面，其表面露出的脊的电阻率低的N型硅，并且槽中的填充材料也暴露在表面。施加大面积金属接触，其延伸穿过表面并与所有脊的低电阻率N型硅欧姆接触。

9. 发明授权

US07244970B2 Low capacitance two-terminal barrier controlled TVS diodes 有权
标题翻译：低电容两端势垒控制TVS二极管
公开(公告)号：US07244970B2
公开(公告)日：2007-07-17
申请号：US11020507
申请日：2004-12-22
申请人： Adrian I. Cogan , Jin Qiu , Richard A. Blanchard
发明人： Adrian I. Cogan , Jin Qiu , Richard A. Blanchard
IPC分类号： H01L29/72
CPC分类号： H01L29/66136 , H01L27/0255 , H01L29/861
摘要： A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.
摘要翻译：两端势垒控制TVS二极管具有消耗区域阻挡阻挡多数载流子流过阴极区附近的沟道区域，该偏压电平低于施加在阳极电极和阴极电极之间的预定钳位电压的偏置电平，并且可布置使得阳极区域在半导体结构的导通期间通过将少数载流子注入沟道区域来提供导电性调制。在目前优选的形式中，多数载流子是电子，而少数载流子是空穴。描述制造方法。

10. 发明授权

US06181541B2 Transistor-PTC circuit protection devices 失效
标题翻译：晶体管 - PTC电路保护器件
公开(公告)号：US06181541B2
公开(公告)日：2001-01-30
申请号：US09177795
申请日：1998-10-22
申请人： Shukri Souri , Hugh Duffy , Adrian I. Cogan , Mark Munch , Nick Nickols
发明人： Shukri Souri , Hugh Duffy , Adrian I. Cogan , Mark Munch , Nick Nickols
IPC分类号： H02H504
CPC分类号： H02H3/025 , H02H5/042 , H02H9/026 , H03K17/0822 , H03K2017/0806
摘要： A circuit protection device for protecting an electrical load includes a three-terminal switch element such as a bipolar, or junction or metal-oxide-semiconductor field effect, transistor and a positive temperature compensation (PTC) resistor. In several embodiments the PTC resistor is in series with the current-carrying electrodes of the transistor. In other embodiments the PTC resistor, or a second PTC resistor, is connected to a control element of the transistor. Both DC and AC load-protection circuits are described.
摘要翻译：用于保护电负载的电路保护装置包括诸如双极或结或金属氧化物半导体场效应的三端开关元件，晶体管和正温度补偿（PTC）电阻器。在几个实施例中，PTC电阻器与晶体管的载流电极串联。在其他实施例中，PTC电阻器或第二PTC电阻器连接到晶体管的控制元件。描述直流和交流负载保护电路。

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