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1. 发明授权

US06696726B1 Vertical MOSFET with ultra-low resistance and low gate charge 有权
标题翻译：具有超低电阻和低栅极电荷的垂直MOSFET
公开(公告)号：US06696726B1
公开(公告)日：2004-02-24
申请号：US09640955
申请日：2000-08-16
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/42368
摘要： A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.
摘要翻译：垂直沟槽双扩散金属氧化物半导体（DMOS）场效应晶体管，其特征在于降低的漏极 - 源极电阻和较低的栅极电荷，并提供高跨导和增强的频率响应。

2. 发明授权

US08710584B2 FET device having ultra-low on-resistance and low gate charge 有权
标题翻译： FET器件具有超低导通电阻和低栅极电荷
公开(公告)号：US08710584B2
公开(公告)日：2014-04-29
申请号：US13344269
申请日：2012-01-05
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate, the substrate being heavily doped and of a first conductivity type, a substrate cap region disposed on the substrate, the substrate cap region being heavily doped and of the first conductivity type and a body region disposed on the substrate cap region, the body region being lightly doped and of a second conductivity type. The MOSFET also includes a trench extending into the body region, a source region of the first conductivity type disposed in the body region and in contact with an upper portion of a sidewall of the trench and an out-diffusion region of the first conductivity type formed such that a spacing between the source region and the out-diffusion region defines a channel region of the MOSFET extending along the sidewall of the trench.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括衬底，衬底被重掺杂并具有第一导电类型，衬底帽区域设置在衬底上，衬底帽区域被重掺杂并且具有第一导电类型以及设置在所述基板盖区域上的主体区域，所述主体区域被轻掺杂并具有第二导电类型。 MOSFET还包括延伸到体区的沟槽，设置在体区中并与沟槽的侧壁的上部接触的第一导电类型的源区和形成的第一导电类型的扩散区使得源极区域和外扩散区域之间的间隔限定沿着沟槽的侧壁延伸的MOSFET的沟道区域。

3. 发明申请

US20120171828A1 Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US20120171828A1
公开(公告)日：2012-07-05
申请号：US13344269
申请日：2012-01-05
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

4. 发明授权

US08101484B2 Method of forming a FET having ultra-low on-resistance and low gate charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US08101484B2
公开(公告)日：2012-01-24
申请号：US12821590
申请日：2010-06-23
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

5. 发明申请

US20100258864A1 Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US20100258864A1
公开(公告)日：2010-10-14
申请号：US12821590
申请日：2010-06-23
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

6. 发明授权

US07745289B2 Method of forming a FET having ultra-low on-resistance and low gate charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US07745289B2
公开(公告)日：2010-06-29
申请号：US10997818
申请日：2004-11-24
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

7. 发明申请

US20100264487A1 Method of Manufacturing a Trench Transistor Having a Heavy Body Region 有权
标题翻译：具有重体区域的沟槽晶体管的制造方法
公开(公告)号：US20100264487A1
公开(公告)日：2010-10-21
申请号：US12755966
申请日：2010-04-07
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

8. 发明授权

US07148111B2 Method of manufacturing a trench transistor having a heavy body region 有权
标题翻译：制造具有重体区域的沟槽晶体管的方法
公开(公告)号：US07148111B2
公开(公告)日：2006-12-12
申请号：US10927788
申请日：2004-08-27
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean E. Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean E. Probst
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

9. 发明申请

US20090134458A1 Method of Manufacturing a Trench Transistor Having a Heavy Body Region 有权
标题翻译：具有重体区域的沟槽晶体管的制造方法
公开(公告)号：US20090134458A1
公开(公告)日：2009-05-28
申请号：US12329509
申请日：2008-12-05
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L29/10
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

10. 发明授权

US06828195B2 Method of manufacturing a trench transistor having a heavy body region 有权
标题翻译：制造具有重体区域的沟槽晶体管的方法
公开(公告)号：US06828195B2
公开(公告)日：2004-12-07
申请号：US10347254
申请日：2003-01-17
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

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