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    • 38. 发明授权
    • Compiler architecture for cross-module optimization
    • 用于交叉模块优化的编译器架构
    • US5375242A
    • 1994-12-20
    • US128385
    • 1993-09-29
    • Rajiv KumarPaul Chan
    • Rajiv KumarPaul Chan
    • G06F9/45
    • G06F8/443
    • An improved compilation and linkage system for use in operating a computer to generate a cross-module optimized executable code file from a plurality of source files and object files. The source files are compiled to intermediate code files using a compiler sub-system. In the preferred embodiment of the present invention, the intermediate code files consist of intermediate language instructions that can be optimized for execution on a predetermined computer and a global symbol table. The compiler sub-system can also be used to generate conventional object code files if desired. A linkage sub-system is then used to cross-module optimize the code in a plurality of intermediate code files and link the resultant object code with any other object code files to generate the executable code file for execution on the computer in question. To the programmer, the operation of the compiler and linkage sub-systems of the present invention is essentially indistinguishable from that of a conventional compiler and linkage sub-system that lacks cross-module optimization.
    • 一种用于操作计算机以从多个源文件和目标文件生成跨模块优化的可执行代码文件的改进的编译和链接系统。 使用编译器子系统将源文件编译为中间代码文件。 在本发明的优选实施例中,中间代码文件由可以在预定计算机上执行的中间语言指令和全局符号表组成。 如果需要,编译器子系统也可以用于生成传统的目标代码文件。 然后使用联动子系统对多个中间代码文件中的代码进行交叉模块优化,并将所得到的目标代码与任何其他目标代码文件进行链接,以生成用于在所讨论的计算机上执行的可执行代码文件。 对于程序员来说,本发明的编译器和连接子系统的操作与缺少交叉模块优化的常规编译器和连接子系统的操作基本上是不可区分的。
    • 40. 发明授权
    • Memory device and method of writing data to a memory device
    • 存储器件和将数据写入存储器件的方法
    • US08780615B2
    • 2014-07-15
    • US13422906
    • 2012-03-16
    • Naveen BatraRajiv KumarSaurabh Agrawal
    • Naveen BatraRajiv KumarSaurabh Agrawal
    • G11C11/00
    • G11C7/12G11C8/08G11C11/413
    • In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
    • 在存储器件中,位线写入电压被施加到第一位线。 将字线电压施加到第一字线,以将数据写入连接到第一字线和第一位线的第一存储器单元。 第一位线和第二位线被电连接用于第一位线和第二位线之间的电荷共享。 在电连接第一位线和第二位线之后的预定时间,第一和第二位线被电断开,并且位线写入电压被施加到第二位线。 字线电压被施加到第二字线,用于将数据写入连接到第二字线和第二位线的第二存储器单元。