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31. 发明申请

US20090261882A1 Skewed Double Differential Pair Circuit for Offset Cancelllation 有权
标题翻译：用于偏移消除的偏斜双差分电路
公开(公告)号：US20090261882A1
公开(公告)日：2009-10-22
申请号：US12494642
申请日：2009-06-30
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden (Clay) Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone , Benjamin T. Voegeli
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden (Clay) Cranford, JR. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone , Benjamin T. Voegeli
IPC分类号： H03L5/00
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.
摘要翻译：公开了一种使用双差分输入对系统产生具有偏移消除的差分信号的差分系统。它使用两个有意偏斜的并联差分晶体管对。名义上，差分对在每个方向相反的方向上倾斜，但是具有相等的幅度，使得两个差分对的组合被名义上平衡。然后，使用用于在系统的校准模式中为第一和第二差分输入提供等电位值的选择装置，增加或减少通过每个差分对的电流，直到任何偏移被充分抵消为止，以及用于比较第一和第第二差分输出在校准模式下确定系统的偏移。

32. 发明申请

US20080186051A1 FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元
公开(公告)号：US20080186051A1
公开(公告)日：2008-08-07
申请号：US11670537
申请日：2007-02-02
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/094
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

33. 发明申请

US20080186054A1 DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元的设计结构
公开(公告)号：US20080186054A1
公开(公告)日：2008-08-07
申请号：US11848470
申请日：2007-08-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，用于示例性多模电路的设计结构可以被配置为以全摆动模式，限定摆动模式，全摆幅至限定摆动转换器模式和限定摆动转换模式中的一种运行，摆动转换器模式。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

34. 发明授权

US07053712B2 Method and apparatus for controlling common-mode output voltage in fully differential amplifiers 有权
标题翻译：用于控制全差分放大器中共模输出电压的方法和装置
公开(公告)号：US07053712B2
公开(公告)日：2006-05-30
申请号：US10710745
申请日：2004-07-30
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Michael A. Sorna , Sebastian T. Ventrone
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Michael A. Sorna , Sebastian T. Ventrone
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/4565 , H03F3/45659 , H03F2200/78 , H03F2203/45418 , H03F2203/45424 , H03F2203/45521
摘要： A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.
摘要翻译：一种用于控制全差分放大器中的共模输出电压的方法包括将全差分放大器的感测共模输出电压与参考电压进行比较，并产生一个误差信号，该误差信号表示检测到的共模输出电压和参考电压。误差信号用于控制包括在全差分放大器内的一个或多个FET器件的体电压，直到检测到的共模输出电压与所述参考电压一致。

35. 发明授权

US08051340B2 System and method for balancing delay of signal communication paths through well voltage adjustment 有权
标题翻译：通过井电压调整来平衡信号通信路径的延迟的系统和方法
公开(公告)号：US08051340B2
公开(公告)日：2011-11-01
申请号：US12136359
申请日：2008-06-10
申请人： Hayden C. Cranford, Jr. , Josep A. Iadanza , Sebastian T. Ventrone
发明人： Hayden C. Cranford, Jr. , Josep A. Iadanza , Sebastian T. Ventrone
IPC分类号： G01R31/28
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

36. 发明申请

US20080229265A1 Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构
公开(公告)号：US20080229265A1
公开(公告)日：2008-09-18
申请号：US12129748
申请日：2008-05-30
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G06F17/5045
摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

37. 发明授权

US07257788B2 Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits 有权
标题翻译：用于将全局时钟选通电路转换为本地时钟门控电路的方法和装置
公开(公告)号：US07257788B2
公开(公告)日：2007-08-14
申请号：US10904397
申请日：2004-11-08
申请人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
发明人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.
摘要翻译：公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

38. 发明申请

US20080240222A1 SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT 有权
标题翻译：通过良好的电压调整来平衡信号通信的延迟的系统和方法
公开(公告)号：US20080240222A1
公开(公告)日：2008-10-02
申请号：US12136359
申请日：2008-06-10
申请人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
发明人： Hayden C. Cranford , Joseph A. Iadanza , Sebastian T. Ventrone
IPC分类号： G01R31/28 , H03K5/159 , H03H7/40 , H03H7/30
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译：在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

39. 发明申请

US20080148204A1 Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
公开(公告)号：US20080148204A1
公开(公告)日：2008-06-19
申请号：US11610963
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

40. 发明授权

US06545521B2 Low skew, power sequence independent CMOS receiver device 失效
标题翻译：低偏移，电源顺序独立的CMOS接收器件
公开(公告)号：US06545521B2
公开(公告)日：2003-04-08
申请号：US09895778
申请日：2001-06-29
申请人： Bret R. Dale , Joseph A. Iadanza , Douglas W. Stout , Sebastian T. Ventrone , Hongfei Wu
发明人： Bret R. Dale , Joseph A. Iadanza , Douglas W. Stout , Sebastian T. Ventrone , Hongfei Wu
IPC分类号： H03L500
CPC分类号： H04L25/0292 , H03K19/00315 , H04L25/0266 , H04L25/0272
摘要： The present invention provides a receiver device having multiple voltage supplies that allows the output stage of the receiver device to go to a safe state whenever its voltage is disconnected or powered-down, independent of any of its normal control circuits. Furthermore, the isolation of the multiple voltage supplies provides a low skew at the output of the receiver device.
摘要翻译：本发明提供了一种具有多个电压源的接收机设备，每当其电压断开或掉电时，接收机设备的输出级都能够进入安全状态，独立于其任何正常的控制电路。此外，多个电压源的隔离在接收器件的输出处提供低偏移。

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