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31. 发明公开

EP3087610A1 HETEROGENEOUS POCKET FOR TUNNELING FIELD EFFECT TRANSISTORS (TFETS) 审中-公开
标题翻译： HETEROGENEOUS BAG FOR隧道场效应晶体管（TFET）
公开(公告)号：EP3087610A1
公开(公告)日：2016-11-02
申请号：EP13900282.8
申请日：2013-12-23
申请人： Intel Corporation
发明人： AVCI, Uygar E. , KOTLYAR, Roza , DEWEY, Gilbert , CHU-KUNG, Benjamin , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/125 , G11C5/06 , H01L29/0669 , H01L29/165 , H01L29/205 , H01L29/7391 , H01L29/7831
摘要： Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

32. 发明公开

EP2619797A2 NON-PLANAR DEVICE HAVING UNIAXIALLY STRAINED FIN AND METHOD OF MAKING SAME 审中-公开
标题翻译：单轴非平面器件WRAPPED FIN及其制备方法
公开(公告)号：EP2619797A2
公开(公告)日：2013-07-31
申请号：EP11827279.8
申请日：2011-09-19
申请人： Intel Corporation
发明人： CEA, Stephen M. , KOTLYAR, Roza , KAVALIEROS, Jack T. , GILES, Martin D. , GHANI, Tahir , KUHN, Kelin J. , KUHN, Markus , ZELICK, Nancy M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

33. 发明公开

EP4040503A1 NON-PLANAR DEVICE HAVING UNIAXIALLY STRAINED FIN AND METHOD OF MAKING SAME 审中-公开
公开(公告)号：EP4040503A1
公开(公告)日：2022-08-10
申请号：EP22160872.2
申请日：2011-09-19
申请人： Intel Corporation
发明人： CEA, Stephen M. , KOTLYAR, Roza , KAVALIEROS, Jack T. , GILES, Martin D. , GHANI, Tahir , KUHN, Kelin J. , KUHN, Markus , ZELICK, Nancy M.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10
摘要： A method and a device made according to the method. The method comprises providing a substrate base portion (102) and a substrate fin (107) extending from the substrate base portion, the fin comprising silicon and germanium; a gate structure (132) covers the fin and epitaxial source and drains (140, 142) comprising germanium are epitaxially grown in recesses formed on both sides of the gate.

34. 发明公开

EP3127164A1 P-TUNNELING FIELD EFFECT TRANSISTOR DEVICE WITH POCKET 审中-公开
标题翻译： P-TUNNELUNG-FELDEFFEKTTRANSISTORVORRICHTUNG MIT TASCHE
公开(公告)号：EP3127164A1
公开(公告)日：2017-02-08
申请号：EP14887274.0
申请日：2014-03-27
申请人： Intel Corporation
发明人： AVCI, Uygar E. , KOTLYAR, Roza , YOUNG, Ian A.
IPC分类号： H01L29/88 , H01L29/78 , H01L21/18
CPC分类号： H01L29/66977 , G06F3/041 , H01L21/18 , H01L23/66 , H01L29/165 , H01L29/205 , H01L29/42312 , H01L29/66356 , H01L29/66742 , H01L29/7391 , H01L29/78 , H01L29/78618 , H01L29/78681 , H01L29/78696 , H01L29/88 , H01L2223/6677
摘要： Described is a tunneling field effect transistor (TFET), comprising: a drain region having a first conductivity type; a source region having a second conductivity type opposite of the first conductivity type; a gate region to cause formation of a channel region between the source and drain regions; and a pocket disposed near a junction of the source region, wherein the pocket region formed from a material having lower percentage of one type of atom than percentage of the one type of atom in the source, channel, and drain regions.
摘要翻译：描述了隧道场效应晶体管（TFET），包括：具有第一导电类型的漏极区; 源极区，具有与第一导电类型相反的第二导电类型; 栅极区域，用于在源区和漏区之间形成沟道区; 以及设置在所述源极区域的接合点附近的口袋，其中所述口袋区域由具有比所述源极，沟道和漏极区域中的一种类型的原子的百分比低的一种类型的原子的比例的材料形成。

35. 发明公开

EP3050079A1 METHODS OF FORMING LOW BAND GAP SOURCE AND DRAIN STRUCTURES IN MICROELECTRONIC DEVICES 审中-公开
标题翻译：法源和漏结构与微电子安排低带隙的形成
公开(公告)号：EP3050079A1
公开(公告)日：2016-08-03
申请号：EP13894549.8
申请日：2013-09-26
申请人： Intel Corporation
发明人： RIOS, Rafael , KOTLYAR, Roza , KUHN, Kelin
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02535 , H01L21/28512 , H01L29/0847 , H01L29/165 , H01L29/401 , H01L29/41725 , H01L29/45 , H01L29/66477 , H01L29/66795
摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.
摘要翻译：形成应变沟道器件利用在源处理完毕的位错的方法/漏结构中描述。这些方法/结构可以包括：形成源极/在装置的基板漏区，并且在源合金的成形/漏区，worin所述合金包含的材料做降低源极/漏极触点和源极之间的带隙/ 漏区基本为零。在实施例减少到装置的外部寄生电阻。

36. 发明公开

EP2878013A1 HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS 审中-公开
标题翻译：高分子GEDEHNTEKANÄLEFÜRFIN-BASIERTE TRANSISTOREN
公开(公告)号：EP2878013A1
公开(公告)日：2015-06-03
申请号：EP13822277.3
申请日：2013-06-12
申请人： Intel Corporation
发明人： CEA, Stephen M. , MURTHY, Anand S. , GLASS, Glenn A. , AUBERTINE, Daniel B. , GHANI, Tahir , KAVALIEROS, Jack T. , KOTLYAR, Roza
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/06 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
摘要翻译：公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三极管等的FinFET）中的技术，其中将应力材料包覆在鳍片的沟道区域上。在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。在一些情况下，可以通过压缩通道中的鳍状物和包覆层的源极/漏极应力器来增强来自包覆层的内置应力。在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。在一个这样的实施例中，硅被提供在SiGe覆层上以改善栅极电介质/半导体界面。

37. 发明公开

EP3127162A1 GERMANIUM TIN CHANNEL TRANSISTORS 有权
标题翻译：锗ZINN-KANALTRANSISTOREN
公开(公告)号：EP3127162A1
公开(公告)日：2017-02-08
申请号：EP14886770.8
申请日：2014-03-27
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , LE, Van , RACHMADY, Willy , KOTLYAR, Roza , RADOSVLJEVIC, Marko , THEN, Han Wui , DASGUPTA, Sansaptak , DEWEY, Gilbert , CHU-KUNG, Benjamin , KAVALIEROS, Jack
IPC分类号： H01L29/78 , H01L27/11
CPC分类号： H01L29/161 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L29/1054 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.
摘要翻译：讨论了与具有锗锡的晶体管和集成电路相关的技术，并入这种晶体管的系统及其形成方法。这种晶体管包括沟道区，其包括鳍的锗锡部分，使得鳍包括设置在衬底上的缓冲层和设置在缓冲层上的锗锡部。

38. 发明公开

EP3123518A1 HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS 审中-公开
标题翻译：富勒姆贝尔斯坦凯恩FÜRFIN-BASIERTE NMOS-TRANSISTOREN
公开(公告)号：EP3123518A1
公开(公告)日：2017-02-01
申请号：EP14887192.4
申请日：2014-03-27
申请人： Intel Corporation
发明人： CEA, Stephen, M. , KOTLYAR, Roza , KENNEL, Harold, W. , GLASS, Glenn, A. , MURTHY, Anand, S. , RACHMADY, Willy , GHANI, Tahir
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L27/0924 , H01L29/045 , H01L29/0649 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66818
摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
摘要翻译：公开了用于将高迁移率应变通道结合到鳍状NMOS晶体管（例如，诸如双栅极，触发器等的FinFET）中的技术，其中将应力材料包覆到鳍的沟道区域上。在一个示例性实施例中，锗或硅锗膜被包覆到硅散热片上，以便在翅片的芯中提供期望的拉伸应变，尽管可以使用其它翅片和包层材料。这些技术与典型的工艺流程兼容，并且包层沉积可以发生在典型工艺流程中的多个位置处。在各种实施例中，可以以最小宽度（或稍后变薄）形成翅片，以便提高晶体管性能。在一些实施例中，变薄的翅片还增加穿过包覆翅片的芯的拉伸应变。在一些情况下，通过添加嵌入式硅外延源和漏极可以进一步增强芯中的应变。

39. 发明公开

EP2920815A1 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 有权
标题翻译：隧道场效应晶体管（TFET）FOR CMOS建筑与PROCESS FOR N型和P型PRODUCING TFET
公开(公告)号：EP2920815A1
公开(公告)日：2015-09-23
申请号：EP13854345.9
申请日：2013-06-12
申请人： Intel Corporation
发明人： KOTLYAR, Roza , CEA, Stephen M. , DEWEY, Gilbert , CHU-KUNG, Benjamin , AVCI, Uygar E. , RIOS, Rafael , CHAUDHRY, Anurag , LINTON, JR., Thomas D. , YOUNG, Ian A. , KUHN, Kelin J.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

40. 发明公开

EP3930005A1 TRANSITION METAL-III-NITRIDE ALLOYS FOR ROBUST HIGH PERFORMANCE HEMTS 审中-公开
公开(公告)号：EP3930005A1
公开(公告)日：2021-12-29
申请号：EP20213612.3
申请日：2020-12-11
申请人： INTEL Corporation
发明人： MURTHY, Anand S. , KOTLYAR, Roza , GLASS, Glenn A. , THEN, Han Wui , CHARUE-BAKKER, Sandrine , EHLERT, Robert , VISHWANATH, Suresh
IPC分类号： H01L29/778 , H01L21/338 , H01L29/201 , H01L29/205 , H01L29/417 , H01L29/423 , H01L29/06 , H01L29/20
摘要： A high electron mobility transistor (HEMT) is disclosed. The HEMT comprises a heterojunction channel that includes a first semiconductor layer (102) and a second semiconductor layer (106) over the first semiconductor layer. A first interface layer (103) is between the first semiconductor layer and the second semiconductor layer, and a second interface layer (105) is over the first interface layer. The HEMT further comprises a source contact (112), a drain contact (112), and a gate contact (114) between the source contact and the drain contact.

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