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1. 发明申请

WO2019139617A1 HETEROJUNCTION BIPOLAR TRANSISTORS HAVING LATERAL GROWTH STRUCTURES 审中-公开
公开(公告)号：WO2019139617A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/013575
申请日：2018-01-12
申请人： INTEL CORPORATION
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/737 , H01L29/66 , H01L29/08
摘要： Heterojunction bipolar transistors having lateral growth structures are disclosed. A disclosed heterojunction bipolar transistor includes a substrate, a dielectric above the substrate, the dielectric having a trench extending therethrough, a collector extending through the trench and above the dielectric, a base laterally extending from the collector, and an emitter laterally extending from the base.

2. 发明申请

WO2019066921A1 GROUP III-NITRIDE LIGHT EMITTING DEVICES INCLUDING A POLARIZATION JUNCTION 审中-公开
公开(公告)号：WO2019066921A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054390
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko
IPC分类号： H01L33/00 , H01L33/04
摘要： Light emitting devices employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge carrier sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening material layer between two III-N material layers. Where a light emitting structure includes a quantum well (QW) structure between two Group III-Nitride polarization junctions, a 2D electron gas (2DEG) induced at a first polarization junction and/or a 2D hole gas (2DHG) induced at a second polarization junction on either side of the QW structure may supply carriers to the QW structure. An improvement in quantum efficiency may be achieved where the intervening material layer further functions as a barrier to carrier recombination outside of the QW structure.

3. 发明申请

WO2019066916A1 COMPLEMENTARY GROUP III-NITRIDE TRANSISTORS WITH COMPLEMENTARY POLARIZATION JUNCTIONS 审中-公开
公开(公告)号：WO2019066916A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054380
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/778 , H01L21/8238 , H01L29/66
摘要： Group III-N transistors of complementary conductivity type employing two polarization junctions of complementary type. Each III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. A III-N heterostructure may include two III-N polarization junctions. A 2D electron gas (2DEG) is induced at a first polarization junction and a 2D hole gas (2DHG) is induced at the second polarization junction. Transistors of complementary type may utilize a separate one of the polarization junctions, enabling III-N transistors to implement CMOS circuitry.

4. 发明申请

WO2019066914A1 TUNNEL POLARIZATION JUNCTION III-N TRANSISTORS 审中-公开
公开(公告)号：WO2019066914A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054373
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak
IPC分类号： H01L29/778 , H01L29/73 , H01L21/8238
CPC分类号： H01L27/0605 , H01L21/8238 , H01L21/8252 , H01L29/045 , H01L29/0847 , H01L29/267 , H01L29/4236 , H01L29/66462 , H01L29/73 , H01L29/778
摘要： Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

5. 发明申请

WO2018236406A1 GROUP III-NITRIDE HETEROSTRUCTURE DIODES 审中-公开
公开(公告)号：WO2018236406A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/039160
申请日：2017-06-24
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/66 , H01L29/861 , H01L21/28 , H01L21/02
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/66212 , H01L29/872
摘要： Diodes employing a Group III-N heterostructure that may provide lower on-resistance for a given diode area relative to conventional III-N diode structures. A III-N heterostructure may include two or more first III-N material layers interleaved with two or more second III-N material layers, thereby forming a heterostructure with three or more heterojunctions. Through control of the III-N material layer composition, a two-dimensional charge sheet (e.g., 2D electron gas) may be induced within each of the first III-N material layers.

6. 发明申请

WO2018125211A1 STACKED GROUP III-NITRIDE TRANSISTORS FOR AN RF SWITCH AND METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2018125211A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069499
申请日：2016-12-30
申请人： INTEL CORPORATION , THEN, Han Wui , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak
发明人： THEN, Han Wui , RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak
IPC分类号： H01L27/24 , H01L29/51 , H01L21/768 , H01L29/778
摘要： A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposed adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

7. 发明申请

WO2018063386A1 TRANSISTOR CONNECTED DIODES AND CONNECTED III-N DEVICES AND THEIR METHODS OF FABRICATION 审中-公开
标题翻译：晶体管连接二极管和连接III-N器件及其制造方法
公开(公告)号：WO2018063386A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054964
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/49 , H01L21/768 , H01L21/764 , H01L29/78
摘要： A transistor connected diode structure is described. In an example, the transistor connected diode structure includes a group III-N semiconductor material disposed on substrate. A raised source structure and a raised drain structure are disposed on the group III-N semiconductor material. A mobility enhancement layer is disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the mobility enhancement layer, the polarization charge inducing layer having a first portion and a second portion separated by a gap. A gate dielectric layer disposed on the mobility enhancement layer in the gap. A first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap. A second metal electrode disposed on the raised source structure.
摘要翻译：描述了晶体管连接的二极管结构。在一个示例中，晶体管连接的二极管结构包括设置在衬底上的III-N族半导体材料。升高的源极结构和升高的漏极结构设置在III-N族半导体材料上。迁移率增强层设置在III-N族半导体材料上。极化电荷感应层设置在迁移率增强层上，极化电荷感应层具有由间隙隔开的第一部分和第二部分。设置在间隙中的迁移率增强层上的栅极电介质层。第一金属电极具有设置在升高的漏极结构上的第一部分，设置在极化电荷感应层的第二部分上方的第二部分和设置在间隙中的栅极电介质层上的第三部分。设置在凸起的源结构上的第二金属电极。

8. 发明申请

WO2018063224A1 InN TUNNEL JUNCTION CONTACTS FOR P-CHANNEL GaN 审中-公开
标题翻译： InN隧道结接点用于P沟道GaN
公开(公告)号：WO2018063224A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054368
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui
IPC分类号： H01L21/02 , H01L29/20 , H01L29/66
CPC分类号： H01L29/2003 , H01L29/0847 , H01L29/0895 , H01L29/205 , H01L29/66522 , H01L29/66545
摘要： Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.
摘要翻译：公开了用于半导体制造的方法和设备。示例装置包括氮化镓（GaN）衬底; 位于GaN衬底上的p型GaN区域; 位于所述GaN衬底上并且与所述p型GaN区共享界面的p型氮化铟（InN）区; 和位于GaN衬底上并且与p型InN区共享界面的n型氮化铟镓（InGaN）区。

9. 发明申请

WO2018004654A1 GROUP III-N TRANSISTORS INCLUDING SOURCE TO CHANNEL HETEROSTRUCTURE DESIGN 审中-公开
标题翻译： III-N族晶体管，包括通道异质结构设计的源
公开(公告)号：WO2018004654A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040690
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/778 , H01L29/66 , H01L21/8238 , H01L29/78
摘要： Techniques are disclosed for forming group III-N transistors including a source to channel heterostructure design. As will be apparent in light of this disclosure, the source to channel heterostructure design may include inserting a relatively high bandgap material layer (e.g., relative to the bandgap of the channel material) between the source and channel of the III-N transistor. In some such embodiments, the relatively high bandgap material layer may be a portion of the polarization charge inducing layer formed over the III-N layer including the channel (e.g., to form a heterojunction/2DEG configuration) that is purposefully left in the source region when forming the source/drain trenches. The source to channel heterostructure design can be used to enhance the high frequency performance of the III-N transistor. Other embodiments may be described and/or disclosed.
摘要翻译：公开了用于形成包括源到沟道异质结构设计的III-N族晶体管的技术。根据本公开内容显而易见的是，沟道异质结构设计的源可以包括在III-N晶体管的源极和沟道之间插入相对高带隙材料层（例如，相对于沟道材料的带隙）。在一些这样的实施例中，相对高带隙材料层可以是在III-N层上方形成的包括沟道（例如，以形成异质结/ 2DEG配置）的极化电荷感应层的一部分，其有目的地留在源极区中当形成源极/漏极沟槽时。通道异质结构设计的来源可用于增强III-N晶体管的高频性能。其他实施例可以被描述和/或公开。

10. 发明申请

WO2018004607A1 CO-INTEGRATION OF GAN AND SELF-ALIGNED THIN BODY GROUP IV TRANSISTORS 审中-公开
标题翻译：甘与自对准薄型第IV族晶体管的集成
公开(公告)号：WO2018004607A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040443
申请日：2016-06-30
申请人： INTEL CORPORATION
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , GARDNER, Sanaz K. , AGABABOV, Pavel M.
IPC分类号： H01L27/06 , H01L29/45 , H01L21/8252 , H01L21/8238
CPC分类号： H01L27/1207 , H01L21/8258 , H01L27/092 , H01L29/2003 , H01L29/7786
摘要： Techniques are disclosed for forming integrated circuits configured with co-integrated group III-N transistors and group IV transistors. The diverse transistors can be formed in a neighboring fashion or otherwise adjacent to one another on a common substrate. The substrate is a semiconductor-on-insulator configuration. According to an embodiment, structural features of neighboring III-N transistors are used to define structural features of an intervening group IV transistor. So, for example, features of the III-N transistor structures are initially used as a mask to pattern the intervening group IV transistor structure and subsequently are later used as part of the III-N transistor structures, in some cases. In other cases, the III-N transistor structures are sacrificial in nature, in that they are removed after formation of the IV transistor feature. The self-aligned co-location techniques can be used to significantly reduce integration processing needed to form mixed transistor technology (e.g., silicon-containing transistors between GaN transistors).
摘要翻译：公开了用于形成配置有共同集成的III-N族晶体管和IV族晶体管的集成电路的技术。不同的晶体管可以以相邻的方式形成或以其他方式在共同的衬底上彼此相邻。衬底是绝缘体上半导体结构。根据一个实施例，使用相邻III-N晶体管的结构特征来定义居间IV族晶体管的结构特征。因此，例如，在一些情况下，III-N晶体管结构的特征最初被用作掩模来图案化插入的IV族晶体管结构，并随后被用作III-N晶体管结构的一部分。在其他情况下，III-N晶体管结构本质上是牺牲的，因为它们在形成IV晶体管特征之后被去除。自对准协同定位技术可用于显着减少形成混合晶体管技术（例如，GaN晶体管之间的含硅晶体管）所需的集成处理。

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