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31. 发明申请

US20110309422A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110309422A1
公开(公告)日：2011-12-22
申请号：US13051516
申请日：2011-03-18
申请人： Masato ENDO , Mitsuhiro Noguchi
发明人： Masato ENDO , Mitsuhiro Noguchi
IPC分类号： H01L29/78
CPC分类号： H01L27/105 , H01L27/0629 , H01L27/11531 , H01L28/20
摘要： According to one embodiment, a semiconductor device includes a first resistance element including a first conductive material, an inter-gate insulation film formed on both ends of the first conductive material in a first direction, and a second conductive material formed above the first conductive material and configured to connect with the first conductive material via a first connection region from which the inter-gate insulation film is removed, and a second resistance element including a third conductive material, the inter-gate insulation film formed on both ends of the third conductive material in the first direction, and a fourth conductive material formed above the third conductive material and configured to connect with the third conductive material via a second connection region from which the inter-gate insulation film is removed, wherein a length of the second connection region is greater than a length of the first connection region in the first direction.
摘要翻译：根据一个实施例，半导体器件包括第一电阻元件，第一电阻元件包括第一导电材料，在第一方向上形成在第一导电材料的两端上的栅极间绝缘膜和形成在第一导电材料上方的第二导电材料并且被配置为经由去除所述栅极间绝缘膜的第一连接区域与所述第一导电材料连接，以及包括第三导电材料的第二电阻元件，所述栅极间绝缘膜形成在所述第三导电材料在第一方向上形成，第四导电材料形成在第三导电材料之上，并被配置为经由去除栅间绝缘膜的第二连接区域与第三导电材料连接，其中第二连接区域大于第一方向上的第一连接区域的长度。

32. 发明申请

US20100258783A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100258783A1
公开(公告)日：2010-10-14
申请号：US12759107
申请日：2010-04-13
申请人： Mitsuhiko NODA , Mitsuhiro Noguchi , Hiroomi Nakajima , Masato Endo
发明人： Mitsuhiko NODA , Mitsuhiro Noguchi , Hiroomi Nakajima , Masato Endo
IPC分类号： H01L27/11 , H01L21/8239 , H01L45/00
CPC分类号： H01L27/105 , H01L27/1021 , H01L27/1052 , H01L27/24
摘要： A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.
摘要翻译：半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括多个存储器单元，多个存储单元阵列堆叠在半导体衬底上以形成三维结构，第一阱形成在半导体衬底中并具有第一导电类型，元件隔离绝缘膜，其包括比第一阱中的第一阱的底表面浅的底表面，并且埋在半导体衬底中，第二阱包括比第一阱的底表面浅的底表面在第一阱中沿着元件隔离绝缘膜的至少一部分的底表面形成并由具有第二导电类型的杂质和与第一阱电连接的接触线形成。

33. 发明授权

US09070743B2 Semiconductor memory and manufacturing method of the same 有权
标题翻译：半导体存储器及其制造方法相同
公开(公告)号：US09070743B2
公开(公告)日：2015-06-30
申请号：US13413952
申请日：2012-03-07
申请人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
发明人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
IPC分类号： H01L29/788 , H01L21/762 , H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L21/76229 , H01L27/11519 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.
摘要翻译：根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管并且其包括由第二隔离绝缘体围绕的第二有源区。第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

34. 发明申请

US20130062680A1 SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20130062680A1
公开(公告)日：2013-03-14
申请号：US13413952
申请日：2012-03-07
申请人： Yoshiko KATO , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
发明人： Yoshiko KATO , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L21/76229 , H01L27/11519 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.
摘要翻译：根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管并且其包括由第二隔离绝缘体围绕的第二有源区。第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

35. 发明授权

US08395922B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08395922B2
公开(公告)日：2013-03-12
申请号：US13035134
申请日：2011-02-25
申请人： Mitsuhiro Noguchi , Kenji Sawamura , Takeshi Kamigaichi , Katsuaki Isobe
发明人： Mitsuhiro Noguchi , Kenji Sawamura , Takeshi Kamigaichi , Katsuaki Isobe
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C16/0483 , G11C16/26
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。第一读出放大器电路连接到多个第一互连。第二读出放大器电路连接到多个第二互连。互连上表面的高度相等。沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

36. 发明授权

US08327229B2 Data memory system 有权
标题翻译：数据存储系统
公开(公告)号：US08327229B2
公开(公告)日：2012-12-04
申请号：US12818709
申请日：2010-06-18
申请人： Mitsuhiro Noguchi
发明人： Mitsuhiro Noguchi
IPC分类号： G11C29/00
CPC分类号： G11C16/3427 , G06F11/1068 , G11C7/1006 , G11C8/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C19/00 , G11C29/00
摘要： A data memory system is provided which includes a nonvolatile memory cell array, an error correction code generation circuit, an error correction code decoding circuit, and a first circuit. The nonvolatile memory cell array includes a plurality of memory cells which store digital data each having at least a value of “1” or “0” as a charge of a charge accumulation layer included in each memory cell, and use a difference between charges of the accumulation layer as a writing bit or an erasing bit. The nonvolatile memory cell array erases memory cells in units of pages, each page being formed of adjacent memory cells included in the plurality of memory cells.
摘要翻译：提供一种包括非易失性存储单元阵列，纠错码产生电路，纠错码解码电路和第一电路的数据存储系统。非易失性存储单元阵列包括多个存储单元，其存储每个具有至少1或0值的数字数据作为每个存储单元中包含的电荷累积层的电荷，并且使用积累层的电荷之间的差作为写位或擦除位。非易失性存储单元阵列以页为单位擦除存储单元，每页由包含在多个存储单元中的相邻存储单元形成。

37. 发明授权

US08185802B2 Data memory system 有权
标题翻译：数据存储系统
公开(公告)号：US08185802B2
公开(公告)日：2012-05-22
申请号：US12369889
申请日：2009-02-12
申请人： Mitsuhiro Noguchi
发明人： Mitsuhiro Noguchi
IPC分类号： G11C29/00
CPC分类号： G11C16/3427 , G06F11/1068 , G11C7/1006 , G11C8/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C19/00 , G11C29/00
摘要： A data memory system includes a nonvolatile memory cell array which includes a plurality of memory cells, a page adjacently formed by the plurality of memory cells being collectively erased in the nonvolatile memory cell, at least binary pieces of digital data of “1” and “0” being stored as charges of a charge accumulation layer in the memory cell, a programming bit and an erasing bit being formed by a difference between the charges of the charge accumulation layer. And the system includes an error correcting code generation circuit, an error correcting code decoding circuit, and a code conversion circuit.
摘要翻译：一种数据存储器系统包括：非易失性存储单元阵列，其包括多个存储单元，由所述多个存储器单元相邻形成的页面在所述非易失性存储单元中被共同擦除;至少二进制数字数据“1”和“ 0“作为电荷累积层的电荷存储在存储单元中，由电荷累积层的电荷之间的差异形成的编程位和擦除位。该系统包括纠错码产生电路，纠错码解码电路和代码转换电路。

38. 发明申请

US20110230041A1 SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE 失效
标题翻译：半导体存储器件及其制造方法，制造垂直MISFET和垂直MISFET的方法以及制造半导体器件和半导体器件的方法
公开(公告)号：US20110230041A1
公开(公告)日：2011-09-22
申请号：US13150768
申请日：2011-06-01
申请人： Hiraku CHAKIHARA , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
发明人： Hiraku CHAKIHARA , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
IPC分类号： H01L21/283
CPC分类号： H01L29/6675 , H01L21/823885 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7833 , H01L29/78642
摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
摘要翻译：垂直MISFET形成在驱动MISFET和传输MISFET上。垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极插入其间。在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。下半导体层，中间半导体层和上半导体层均由硅膜构成。下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

39. 发明授权

US08008703B2 Nonvolatile semiconductor memory device with twin-well 有权
标题翻译：具有双阱的非易失性半导体存储器件
公开(公告)号：US08008703B2
公开(公告)日：2011-08-30
申请号：US12175201
申请日：2008-07-17
申请人： Mitsuhiro Noguchi , Minori Kajimoto
发明人： Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L29/788
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526
摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.
摘要翻译：非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离，其形成在半导体衬底中。第三井具有比第二井的第二部分更少的深度。

40. 发明授权

US07985678B2 Method of manufacturing a semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US07985678B2
公开(公告)日：2011-07-26
申请号：US12896933
申请日：2010-10-04
申请人： Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
发明人： Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
IPC分类号： H01L21/44
CPC分类号： H01L27/1104 , H01L27/11
摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
摘要翻译：在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二光刻胶膜作为掩模。由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

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