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31. 发明授权

US08435704B2 Mask blank, transfer mask, and methods of manufacturing the same 有权
标题翻译：掩模空白，转印掩模及其制造方法
公开(公告)号：US08435704B2
公开(公告)日：2013-05-07
申请号：US12875783
申请日：2010-09-03
申请人： Osamu Nozawa , Hiroaki Shishido
发明人： Osamu Nozawa , Hiroaki Shishido
IPC分类号： G03F1/22
CPC分类号： G03F1/54 , G03F1/50
摘要： In a mask blank for manufacturing a transfer mask adapted to exposure light having a wavelength of 200 nm or less, the mask blank has a light-shielding film on a transparent substrate. The light-shielding film is made of a material containing tantalum as a main metal component and includes a highly oxidized layer which has an oxygen content of 60 at % or more and which is formed as a surface layer of the light-shielding film, that is placed on a side opposite to a transparent substrate side.
摘要翻译：在用于制造适于曝光波长为200nm以下的光的转印掩模的掩模坯料中，掩模坯料在透明基板上具有遮光膜。遮光膜由含有钽作为主要金属成分的材料制成，并且包含氧含量为60原子％以上且形成为遮光膜的表面层的高度氧化层，放置在与透明基板侧相对的一侧。

32. 发明申请

US20110305978A1 PHOTOMASK BLANK, PHOTOMASK, AND METHOD OF MANUFACTURING PHOTOMASK BLANK 有权
标题翻译： PHOTOMASK BLANK，PHOTOMASK，以及制造光电白皮书的方法
公开(公告)号：US20110305978A1
公开(公告)日：2011-12-15
申请号：US12935766
申请日：2009-03-31
申请人： Hiroyuki Iwashita , Hiroaki Shishido , Atsushi Kominato , Masahiro Hashimoto , Morio Hosoya
发明人： Hiroyuki Iwashita , Hiroaki Shishido , Atsushi Kominato , Masahiro Hashimoto , Morio Hosoya
IPC分类号： G03F1/00
CPC分类号： G03F1/22 , G03F1/46 , G03F1/54 , G03F1/80 , H01L21/0274
摘要： The present invention provides a photomask blank for producing a photomask to which an ArF excimer laser light is applied, wherein: a thin film having a multilayer structure is provided on a light transmissive substrate; and the uppermost layer of the thin film has an amorphous structure made of a material comprising chromium and at least one of nitrogen, oxygen and carbon.
摘要翻译：本发明提供一种用于制造施加了ArF准分子激光的光掩模的光掩模坯料，其中：在透光基板上设置具有多层结构的薄膜; 并且薄膜的最上层具有由包含铬和氮，氧和碳中的至少一种的材料制成的无定形结构。

33. 发明授权

US07365391B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07365391B2
公开(公告)日：2008-04-29
申请号：US11528637
申请日：2006-09-28
申请人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido , Masato Mikawa
发明人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido , Masato Mikawa
IPC分类号： H01L31/00
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.
摘要翻译：提供具有高耐压的半导体器件。活动槽22a包括长而窄的主槽部26和与主槽部的纵向侧面连接的副槽部27以及高度低于底面的第二导电型的埋入区域24 第二导电类型的基底扩散区域32a设置在主槽部分26的底表面上。在子槽部27中设置有与基底扩散区域32a相接触的第二导电类型的活动沟槽填充区域25。埋入区域24通过有源沟槽填充区域25与基极扩散区域32a接触。由于一个栅极沟槽83由一个有源槽22a中的掩埋区域24上方的部分形成，所以栅电极插塞48不分离，这允许电极图案被简化。

34. 发明授权

US07208375B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07208375B2
公开(公告)日：2007-04-24
申请号：US10967657
申请日：2004-10-19
申请人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
发明人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/4238 , H01L29/66348 , H01L29/7397 , H01L29/7811 , H01L29/872
摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
摘要翻译：提供了一种提高晶体管耐破坏性的技术。在本发明的晶体管中，填充区域的高度高于掩埋区域的高度，使得填充区域的耐受电压高于掩埋区域的耐受电压。因此，由于在有源区域发生雪崩击穿，导致雪崩击穿电流流过具有大面积的有源区域，不会发生电流集中。结果，增加了抵抗击穿的元件的坚固性。

35. 发明授权

US06876034B2 Semiconductor device having active grooves 有权
标题翻译：具有有源凹槽的半导体器件
公开(公告)号：US06876034B2
公开(公告)日：2005-04-05
申请号：US10607083
申请日：2003-06-27
申请人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
发明人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/47 , H01L29/739 , H01L29/78 , H01L29/872 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/66348 , H01L29/7397 , H01L29/7811 , H01L29/872
摘要： A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.
摘要翻译：提供了具有均匀填充有半导体填料的槽的半导体器件。每个窄活动槽的两端连接到围绕有源槽的内周槽。有源沟槽两端的半导体填料的生长速度与其中心部分的生长速度相等。结果，获得了具有均匀高度填充有半导体填料的有源沟槽的半导体器件。

36. 发明授权

US5539514A Foreign particle inspection apparatus and method with front and back illumination 失效
标题翻译：具有前后照明的外来颗粒检查装置及方法
公开(公告)号：US5539514A
公开(公告)日：1996-07-23
申请号：US269379
申请日：1994-06-30
申请人： Hiroaki Shishido , Shunichi Matsumoto
发明人： Hiroaki Shishido , Shunichi Matsumoto
IPC分类号： G01N21/94 , G01N21/956 , G01N21/00
CPC分类号： G01N21/956 , G01N21/94
摘要： A method of inspecting a phase shift reticle comprising a transparent or translucent substrate, a circuit pattern of an opaque film formed on the front surface of the substrate and a pattern of a transparent or translucent film formed on the front surface of the substrate comprises: obliquely projecting a front illuminating light beam on the front surface of the substrate by a front illuminating system; concentrating scattered light scattered by the surface of the substrate and the surfaces of the patterns, obliquely projecting a back illuminating light beam on the back surface of the substrate by a back illuminating system, concentrating transmitted-and-diffracted light transmitted and diffracted by the substrate and the patterns; intercepting the scattered light scattered by the patterns and the transmitted-and-diffracted light transmitted and diffracted by the patterns with spatial filters disposed on Fourier transform planes, focusing the scattered light and the transmitted-and-diffracted light transmitted by the spatial filters on detectors; and comparing detection signals provided by the detectors to see if there are any foreign particles on the phase shift reticle.
摘要翻译：检查包括透明或半透明基板的相移掩模版的方法，形成在基板的前表面上的不透明膜的电路图案和形成在基板的前表面上的透明或半透明膜的图案包括：通过前照明系统将前照明光束投影在基板的前表面上; 集中由基板表面和图案表面散射的散射光，通过后照明系统将后照明光束倾斜地投射在基板的背面上，集中由基板透射和衍射的透射衍射光和模式; 截取由图案散射的散射光和通过布置在傅立叶变换平面上的空间滤光片通过图案传输和衍射的透射衍射光，将散射光和由空间滤光器透射的透射衍射光聚焦在检测器 ; 并比较由检测器提供的检测信号，以查看相移掩模版上是否存在任何异物。

37. 发明授权

US08846274B2 Mask blank, transfer mask and process for manufacturing semiconductor devices 有权
标题翻译：掩模空白，传输掩模和制造半导体器件的工艺
公开(公告)号：US08846274B2
公开(公告)日：2014-09-30
申请号：US13605125
申请日：2012-09-06
申请人： Hiroaki Shishido , Osamu Nozawa , Atsushi Kominato
发明人： Hiroaki Shishido , Osamu Nozawa , Atsushi Kominato
IPC分类号： G03F1/00 , G03F1/50
CPC分类号： C03C17/3411 , C03C17/3423 , C03C17/3435 , G03F1/38
摘要： The present invention is the mask blank includes a glass substrate and a thin film formed on a main surface of the glass substrate, the thin film includes a material containing tantalum and substantially no hydrogen, and the mask blank has a invasion suppressive film between the main surface of the glass substrate and the thin film which suppresses hydrogen from being invaded from the glass substrate into the thin film.
摘要翻译：本发明的掩模坯料包括玻璃基板和形成在玻璃基板的主表面上的薄膜，该薄膜包括含有钽并且基本上不含氢的材料，掩模坯料在主体之间具有侵入抑制膜玻璃基板的表面和抑制氢从玻璃基板侵入薄膜的薄膜。

38. 发明申请

US20110111332A1 PHASE SHIFT MASK BLANK AND PHASE SHIFT MASK 有权
标题翻译：相移屏蔽层和相位移屏蔽
公开(公告)号：US20110111332A1
公开(公告)日：2011-05-12
申请号：US13001365
申请日：2009-06-25
申请人： Hiroyuki Iwashita , Hiroaki Shishido , Atsushi Kominato , Masahiro Hashimoto
发明人： Hiroyuki Iwashita , Hiroaki Shishido , Atsushi Kominato , Masahiro Hashimoto
IPC分类号： G03F1/00
CPC分类号： G03F1/58 , G03F1/32
摘要： The present invention provides a photomask blank used for producing a photomask to which an ArF excimer laser light is applied, wherein: a light-shielding film is provided on a light transmissive substrate; the light-shielding film has a laminated structure in which a lower layer, an interlayer and an upper layer are laminated in this order from the side close to the light transmissive substrate; the thickness of the entire light-shielding film is 60 nm or less; the lower layer is made of a film containing a metal and has a first etching rate; the upper layer is made of a film containing a metal and has a third etching rate; the interlayer is made of a film containing the same metal as that contained in the lower layer or the upper layer and has a second etching rate that is lower than the first etching rate and the third etching rate; and the thickness of the interlayer is 30% or less of the thickness of the entire light-shielding film.
摘要翻译：本发明提供一种用于制造施加了ArF准分子激光的光掩模的光掩模坯料，其中：在透光基板上设置有遮光膜; 遮光膜具有层叠结构，其中从靠近透光基底的一侧依次层叠下层，中间层和上层; 整个遮光膜的厚度为60nm以下; 下层由含有金属的膜制成，具有第一蚀刻速率; 上层由含有金属的膜制成，具有第三蚀刻速率; 中间层由含有与下层或上层相同的金属的膜制成，具有比第一蚀刻速度和第三蚀刻速度低的第二蚀刻速率; 并且中间层的厚度为整个遮光膜的厚度的30％以下。

39. 发明授权

US07573109B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07573109B2
公开(公告)日：2009-08-11
申请号：US11528654
申请日：2006-09-28
申请人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
发明人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/47 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7809 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90
摘要翻译：具有高抗破坏性能的半导体器件。半导体器件1包括同心地设置在第一导电类型的电阻层15上的第二导电类型的保护掩埋区域44b，并且在保护掩埋区域44b的内侧设置有基极扩散区域17a，并且设置第二导电类型的基极掩埋区域44a 在基底扩散区域17a的底面上。在相同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为Wm1，不同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为Wm2， 44b是WPE。当Wm1

40. 发明申请

US20070069323A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20070069323A1
公开(公告)日：2007-03-29
申请号：US11528654
申请日：2006-09-28
申请人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
发明人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
IPC分类号： H01L23/58
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/47 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7809 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90
摘要翻译：具有高抗破坏性能的半导体器件。半导体器件1包括同心地设置在第一导电类型的电阻层15上的第二导电类型的保护掩埋区域44b，并且在保护掩埋区域44b的内部设置基极扩散区域17a，并且在第二导电类型的第二导电类型的基极掩埋区域44a 导电类型设置在基底扩散区域17a的底表面上。在相同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为W m 1，在不同的基底扩散区域17的底部的相邻的基底掩埋区域44a之间的距离 a是Wm 2 2，并且防护埋入区域44b之间的距离是W PE 2 。第一导电类型的杂质量Q <1> 1和第二导电类型的杂质量Q 2> 2 的比率包括在最内侧保护埋入区44的宽度方向中心的内侧当Wm <1时，b是0.90 。当W 1 2 时，该比例为Q 2 / Q 1 /SUB><0.92当WM 2 PE 时，该比例为1.10 / Q <1> 。

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