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31. 发明授权

US07927943B2 Method for tuning a work function of high-k metal gate devices 有权
标题翻译：用于调谐高k金属栅极器件功能的方法
公开(公告)号：US07927943B2
公开(公告)日：2011-04-19
申请号：US12488960
申请日：2009-06-22
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成第一和第二晶体管，第一晶体管具有包括第一虚拟栅极的第一栅极结构，第二晶体管具有第二栅极结构包括第二伪栅极，去除第一和第二伪栅极，从而分别形成第一沟槽和第二沟槽，形成第一金属层以部分地填充在第一和第二沟槽中，去除第一沟槽内的第一金属层形成第二金属层以部分地填充在第一和第二沟槽中，形成第三金属层以部分地填充在第一和第二沟槽中，回流第二金属层和第三金属层，以及形成第四金属层以填充在第一和第二个沟槽的剩余部分。

32. 发明授权

US08349732B2 Implanted metal silicide for semiconductor device 有权
标题翻译：用于半导体器件的注入金属硅化物
公开(公告)号：US08349732B2
公开(公告)日：2013-01-08
申请号：US12176133
申请日：2008-07-18
申请人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L29/4983 , H01L21/28518 , H01L21/28525 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.
摘要翻译：提出了一种用于形成金属硅化物的器件和方法。在基板上形成包括栅极区域，源极区域和漏极区域的器件。在基板上设置金属，接着进行第一退火，在栅极区域，源极区域和漏极区域中的至少一个上形成金属硅化物。将未反应的金属从基材上除去。金属硅化物被注入原子。植入物之后是衬底的超退火。

33. 发明授权

US08286114B2 3-dimensional device design layout 有权
标题翻译：三维设备设计布局
公开(公告)号：US08286114B2
公开(公告)日：2012-10-09
申请号：US11833119
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
摘要翻译：提供了一种用于定义诸如finFET的3-D器件的布局的方法。该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

34. 发明申请

US20110260251A1 Semiconductor Device and Method of Fabricating Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260251A1
公开(公告)日：2011-10-27
申请号：US13178755
申请日：2011-07-08
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L27/12
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

35. 发明申请

US20110233682A1 Reducing Device Performance Drift Caused by Large Spacings Between Active Regions 有权
标题翻译：降低活动区域之间大间距引起的设备性能漂移
公开(公告)号：US20110233682A1
公开(公告)日：2011-09-29
申请号：US13155251
申请日：2011-06-07
申请人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L27/088 , H01L27/092 , B82Y99/00
CPC分类号： H01L21/823475 , H01L21/31155 , H01L21/823412 , H01L21/823481 , H01L29/7846
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

36. 发明申请

US20110076813A1 Semiconductor Device with both I/O and Core Components and Method of Fabricating Same 有权
标题翻译：具有I / O和核心组件的半导体器件及其制造方法
公开(公告)号：US20110076813A1
公开(公告)日：2011-03-31
申请号：US12961167
申请日：2010-12-06
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

37. 发明授权

US08624295B2 SRAM devices utilizing strained-channel transistors and methods of manufacture 有权
标题翻译：使用应变通道晶体管的SRAM器件和制造方法
公开(公告)号：US08624295B2
公开(公告)日：2014-01-07
申请号：US12052389
申请日：2008-03-20
申请人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L21/02 , H01L21/762 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.
摘要翻译：提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。绝缘层基本上从半导体衬底表面升高。升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。

38. 发明授权

US08558278B2 Strained transistor with optimized drive current and method of forming 有权
标题翻译：应变晶体管具有优化的驱动电流和成型方法
公开(公告)号：US08558278B2
公开(公告)日：2013-10-15
申请号：US11849798
申请日：2007-09-04
申请人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.
摘要翻译：应变感应层形成在MOS器件的顶部，以增加沟道区中的载流子迁移率。在优选实施例中，应变诱导层的尺寸可导致优化的驱动电流增加和改进的NMOS和PMOS器件中的驱动电流均匀性。优选实施例的优点是在不添加复杂的处理步骤的情况下获得改进的设备性能。优选实施例的另一个优点是附加的处理步骤可以容易地集成到已知的CMOS工艺流程中。此外，创建定义拉伸和压缩应变诱导层的光罩不需要对现有设计数据库进行额外的设计工作。

39. 发明申请

US20120286368A1 Layout Methods of Integrated Circuits Having Unit MOS Devices 有权
标题翻译：具有单位MOS器件的集成电路布局方法
公开(公告)号：US20120286368A1
公开(公告)日：2012-11-15
申请号：US13558109
申请日：2012-07-25
申请人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
摘要翻译：半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

40. 发明申请

US20100013029A1 Structure and a Method of Manufacture for Low Resistance NiSix 有权
标题翻译：低电阻NiSix的结构和制造方法
公开(公告)号：US20100013029A1
公开(公告)日：2010-01-21
申请号：US12176133
申请日：2008-07-18
申请人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L29/4983 , H01L21/28518 , H01L21/28525 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.
摘要翻译：提出了一种用于形成金属硅化物的器件和方法。在基板上形成包括栅极区域，源极区域和漏极区域的器件。在基板上设置金属，接着进行第一退火，在栅极区域，源极区域和漏极区域中的至少一个上形成金属硅化物。将未反应的金属从基材上除去。金属硅化物被注入原子。植入物之后是衬底的超退火。

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