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31. 发明申请

US20070291561A1 SENSE-AMPLIFIER ASSIST (SAA) WITH POWER-REDUCTION TECHNIQUE 审中-公开
标题翻译：具有减少功率的感应放大器辅助（SAA）
公开(公告)号：US20070291561A1
公开(公告)日：2007-12-20
申请号：US11424072
申请日：2006-06-14
申请人： Geordie M. Braceras , Harold Pilo , Fred J. Towter
发明人： Geordie M. Braceras , Harold Pilo , Fred J. Towter
IPC分类号： G11C7/06
CPC分类号： G11C7/12 , G11C7/06 , G11C11/41 , G11C11/419 , G11C29/08
摘要： The present invention provides an apparatus and method to reduce the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring Sense Amplifier Assist (SAA) circuitry. In particular, the present invention is an apparatus and method that limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.
摘要翻译：本发明提供一种降低存储器件功率的装置和方法，特别是具有感测放大器辅助（SAA）电路的静态随机存取存储器（SRAM）阵列。特别地，本发明是将SAA电路的实现限于不符合应用电压要求的SRAM阵列块的装置和方法。

32. 发明授权

US07180320B2 Adaptive integrated circuit based on transistor current measurements 失效
标题翻译：基于晶体管电流测量的自适应集成电路
公开(公告)号：US07180320B2
公开(公告)日：2007-02-20
申请号：US10995791
申请日：2004-11-23
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G01R31/26
CPC分类号： G01R31/3004
摘要： BUR920020148US13 A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.
摘要翻译：一种对集成电路芯片上的集成电路进行调谐的方法，包括：在集成电路芯片上的一个或多个测试场效应晶体管的饱和测量时执行漏极电流; 基于饱和度测量时的漏极电流有选择地对集成电路芯片上的熔丝组进行熔丝; 并根据保险丝库中的熔断和未熔断保险丝的模式调整集成电路的输出。

33. 发明授权

US07016251B2 Method and apparatus for initializing SRAM device during power-up 失效
标题翻译：上电期间初始化SRAM器件的方法和装置
公开(公告)号：US07016251B2
公开(公告)日：2006-03-21
申请号：US10710707
申请日：2004-07-29
申请人： John A. Gabric , Harold Pilo
发明人： John A. Gabric , Harold Pilo
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/12 , G11C11/413
摘要： A method for initializing a static random access memory (SRAM) device during power-up includes clamping one of a pair of bitlines of the SRAM device to a logic low potential while allowing the other of the pair of bitlines to be coupled to a charging logic high potential. An SRAM storage cell within the SRAM device is forced to a stable state by selectively allowing a wordline potential of a wordline associated with the SRAM storage cell to follow the charging logic high potential, thereby coupling the SRAM storage cell to the pair of bitlines.
摘要翻译：用于在上电期间初始化静态随机存取存储器（SRAM）器件的方法包括将SRAM器件的一对位线中的一个钳位到逻辑低电位，同时允许该对位线中的另一个耦合到充电逻辑高潜力 SRAM器件中的SRAM存储单元通过选择性地允许与SRAM存储单元相关联的字线的字线电位跟随充电逻辑高电位而强制进入稳定状态，从而将SRAM存储单元耦合到该对位线。

34. 发明授权

US06999547B2 Delay-lock-loop with improved accuracy and range 失效
标题翻译：延迟锁定循环具有提高的精度和范围
公开(公告)号：US06999547B2
公开(公告)日：2006-02-14
申请号：US10065840
申请日：2002-11-25
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： H04L7/033
CPC分类号： H03L7/00
摘要： A Delay-Lock-Loop circuit and a method for producing a phase shift comprises a phase generator producing a first and second clock signal having a first and second rising edge, respectively, wherein a timing difference between the first and second rising edges is equal to a desired cycle time; a delay circuit operable to receive the first clock signal and to produce a delayed clock signal; and a latch element connected to the delay circuit, and operable to check whether the delayed clock signal is delayed by an amount equal to the desired cycle time; a plurality of serially connected binary-weighted inverters connected to the latch element, which are operable to adjust the delay of the delayed clock signal to be equal to the desired cycle time; and a phase-shifted delay circuit connected to the delay circuit, and operable to produce multiple degrees of phase shift of the delayed clock signal.
摘要翻译：延迟锁定环电路和产生相移的方法包括相位发生器，分别产生具有第一和第二上升沿的第一和第二时钟信号，其中第一和第二上升沿之间的定时差等于期望的周期时间; 延迟电路，其可操作以接收所述第一时钟信号并产生延迟的时钟信号; 以及锁存元件，连接到所述延迟电路，并且可操作以检查延迟的时钟信号是否被延迟等于期望周期时间的量; 连接到所述锁存元件的多个串行连接的二进制加权反相器，其可操作以将延迟的时钟信号的延迟调整为等于期望的周期时间; 以及连接到所述延迟电路的相移延迟电路，并且可操作以产生延迟的时钟信号的多个相移。

35. 发明申请

US20050207210A1 Apparatus and Method for Small Signal Sensing in an SRAM Cell Utilizing PFET Access Devices 失效
标题翻译：在使用PFET接入设备的SRAM单元中小信号感测的装置和方法
公开(公告)号：US20050207210A1
公开(公告)日：2005-09-22
申请号：US10708713
申请日：2004-03-19
申请人： John Barth , George Braceras , Harold Pilo
发明人： John Barth , George Braceras , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.
摘要翻译：在静态随机存取存储器（SRAM）单元的读取操作期间用于小信号感测的方法包括将一对互补读出放大器数据线耦合到与SRAM单元相关联的对应的一对互补位线，并且将读出放大器设置为放大在感测放大器数据线上产生的信号，其中位线对在读出放大器设置时保持耦合到读出放大器数据线。

36. 发明授权

US06912165B2 Method for transparent updates of output driver impedance 失效
标题翻译：输出驱动器阻抗的透明更新方法
公开(公告)号：US06912165B2
公开(公告)日：2005-06-28
申请号：US10604867
申请日：2003-08-22
申请人： Phillip L. Corson , Harold Pilo
发明人： Phillip L. Corson , Harold Pilo
IPC分类号： G11C5/00 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/419
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C11/419 , G11C2207/2254
摘要： Disclosed is a method and structure that controls an output driver by generating an output data path clock signal from a system clock signal and timing the programmable impedance of the output driver according to the output data path clock signal. The method/structure controls the timing of the line driver circuits according to the output data path clock signal. By timing the programmable impedance according to the output data path clock signal, the timing of delivery of an impedance control signal is coordinated with the timing of delivery of data. The method/structure also performs impedance updates on the output driver more frequently during initialization cycles than in cycles that occur after the initialization cycles expire using at least two differently timed clock dividers and a counter.
摘要翻译：公开了一种通过从系统时钟信号产生输出数据路径时钟信号并根据输出数据路径时钟信号对输出驱动器的可编程阻抗进行定时来控制输出驱动器的方法和结构。该方法/结构根据输出数据路径时钟信号来控制线路驱动电路的定时。通过根据输出数据路径时钟信号对可编程阻抗进行定时，将阻抗控制信号的传递时序与数据传送的时序协调。该方法/结构还在初始化周期期间更频繁地对输出驱动器进行阻抗更新，而不是在使用至少两个不同时间的时钟分频器和计数器的初始化周期到期后发生的周期。

37. 发明申请

US20050046441A1 SCALABLE TERMINATION 失效
标题翻译：可扩展终止
公开(公告)号：US20050046441A1
公开(公告)日：2005-03-03
申请号：US10604936
申请日：2003-08-27
申请人： George Braceras , Reid Hutchins , Harold Pilo
发明人： George Braceras , Reid Hutchins , Harold Pilo
IPC分类号： H04L25/02 , H03K19/003
CPC分类号： H04L25/0298 , H04L25/0278
摘要： In a first aspect, a first method is provided for providing multiple termination values using a plurality of binary termination signals. The first method includes the steps of (1) determining a characteristic impedance of a first port by generating a plurality of binary termination signals; and (2) modifying a characteristic impedance of a second port by manipulating one or more of the plurality of binary termination signals. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种使用多个二进制终止信号来提供多个终止值的第一方法。第一种方法包括以下步骤：（1）通过产生多个二进制终止信号来确定第一端口的特性阻抗; 和（2）通过操纵多个二进制终止信号中的一个或多个来修改第二端口的特性阻抗。提供了许多其他方面。

38. 发明授权

US06504766B1 System and method for early write to memory by injecting small voltage signal 失效
标题翻译：通过注入小电压信号来早期写入存储器的系统和方法
公开(公告)号：US06504766B1
公开(公告)日：2003-01-07
申请号：US09896734
申请日：2001-06-29
申请人： Harold Pilo , John E. Barth, Jr.
发明人： Harold Pilo , John E. Barth, Jr.
IPC分类号： G11C1604
CPC分类号： G11C7/062 , G11C7/18 , G11C11/4091 , G11C11/4094
摘要： A system and method is disclosed for writing early within a memory cycle by injecting a small voltage difference signal prior to setting a sense amplifier, and thereafter setting the sense amplifier which amplifies the small voltage signal to predetermined high and low voltage logic levels for writing to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. Local bitswitches apply first and second write voltages having a small voltage difference to a true bitline and a reference bitline prior to setting the sense amplifier.
摘要翻译：公开了一种系统和方法，用于在设置感测放大器之前通过注入小电压差信号在存储器周期内早期写入，然后设置将小电压信号放大到预定的高电压和低电压逻辑电平以便写入的读出放大器存储单元。以这种方式，写入可以在读取的同一时间内完成，而不会在存储器中的相邻位线上的数据损坏风险。在设置读出放大器之前，本地位开关将具有小电压差的第一和第二写入电压应用于真位置线和参考位线。

39. 发明授权

US06392949B2 High performance memory architecture 有权
公开(公告)号：US06392949B2
公开(公告)日：2002-05-21
申请号：US09761460
申请日：2001-01-16
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G11C300
CPC分类号： G11C11/417 , G11C7/1039 , G11C11/418
摘要： A high performance memory array architecture is provided to minimize the delays within each array. The architecture of the array equalizes the access time to all memory elements by optimizing the positioning of the subarrays with respect to buffering and rebuffering elements used in the array which cause delays.

40. 发明授权

US06327224B1 On-chip method for measuring access time and data-pin spread 失效
标题翻译：用于测量访问时间和数据引脚扩展的片上方法
公开(公告)号：US06327224B1
公开(公告)日：2001-12-04
申请号：US09595632
申请日：2000-06-16
申请人： Geordie Maria Braceras , Harold Pilo , Dale E. Pontius
发明人： Geordie Maria Braceras , Harold Pilo , Dale E. Pontius
IPC分类号： G04F1000
CPC分类号： G01R31/31858 , G11C29/50
摘要： An on-chip I/O timings measurement circuit that improves measurement accuracy compared to conventional external test methods. This circuit guarantees AC timing specifications that are too small for the measurement capabilities of today's high-frequency memory testers. This system in incorporated into the SRAM via the JTAG interface and a JTAG private instruction. A private instruction refers to an unused instruction from the industry-standard public instruction set. Private instructions are usually reserved for the manufacturer, but may be provided to the user as an enhancement to the standard JTAG instruction set.
摘要翻译：一种片上I / O时序测量电路，与传统的外部测试方法相比，可提高测量精度。该电路保证对当今高频记忆体测试仪的测量能力太小的交流定时规格。该系统通过JTAG接口和JTAG专用指令并入SRAM。私有指令是指来自行业标准公共指令集的未使用指令。私有指令通常为制造商保留，但可作为标准JTAG指令集的增强提供给用户。

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