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31. 发明专利

JP2589713B2 失效
公开(公告)号：JP2589713B2
公开(公告)日：1997-03-12
申请号：JP29380987
申请日：1987-11-20
申请人： HITACHI LTD
发明人： MASUDA SATOSHI , KAWASAKI IKUYA , MATSUI SHIGESUMI
IPC分类号： G06F11/28 , G06F11/26 , G06F11/34 , G06F11/36 , G06F12/08 , G06F12/10 , G06F15/78

32. 发明专利

JPH08320829A DATA PROCESSOR 失效
公开(公告)号：JPH08320829A
公开(公告)日：1996-12-03
申请号：JP24087395
申请日：1995-08-25
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , NARITA SUSUMU , TAMAKI SANEAKI , KAWASAKI IKUYA
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F12/14 , G11C29/24
摘要： PURPOSE: To access an address conversion buffer by an MOV instruction and perform operation for invalidating an entry, etc., by comparing retrieved address information that an entry of a specified area has with the information that write data has. CONSTITUTION: For write access to a cache memory CACHE-M or address conversion buffer TLB, address information for specifying an object to be written is stored in a register R1 according to a specific address format. Then the data transfer MOV instruction is executed and then while the data in a register R0 is regarded as a transfer source, the data are written at the address position of the cache memory CACHE-M or address conversion buffer TLB specified by the register R1. Supporting associative writing guarantees the operation for invalidating an entry without fail since the retrieved address information which is not considered only by address specification are regarded as a condition of whether or not writing is enabled.

33. 发明专利

JPH0895943A MICROPROCESSOR 失效
公开(公告)号：JPH0895943A
公开(公告)日：1996-04-12
申请号：JP25139494
申请日：1994-09-20
申请人： HITACHI LTD
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , NARITA SUSUMU , NEMOTO MASATO
IPC分类号： G06F12/06 , G06F3/08 , G06F13/38 , G06F15/78
摘要： PURPOSE: To improve convenience in use by loading a personal computer memory card international association(PCMCIA) interface on a bus state controller for outputting a control signal corresponding to the division of a physical address space and various memory and bus interface specifications. CONSTITUTION: A bus state controller BSC outputs the control signal corresponding to the division of the physical address space and the various memory and bus state interface specifications. The PCMCIA interface is loaded on this bus state controller BSC. Thus, the microprocessor can be directly connected with an IC memory card and an I/O card as well, the system of various kinds of information equipment using the microprocessor can be easily designed, data can be transferred at a high speed by the compact system at the same time, and the microprocessor is made convenient for miniaturized portable information equipment.

34. 发明专利

JPH07200402A DATA PROCESSOR 失效
公开(公告)号：JPH07200402A
公开(公告)日：1995-08-04
申请号：JP463695
申请日：1995-01-17
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： NISHIMUKAI TADAHIKO , HASEGAWA ATSUSHI , UCHIYAMA KUNIO , KAWASAKI IKUYA , HANAWA MAKOTO
IPC分类号： G06F12/08
摘要： PURPOSE:To provide the data processor whose functions can easily be tested from outside the chip. CONSTITUTION:The data processor is equipped with a purge control circuit 6 which outputs a purge command signal 162 in response to a next instruction request signal 141 while an external purge signal 161 is supplied from outside the data processor, and the contents of an instruction cache memory 31 are invalidated according to the purge command signal 162. The contents of the instruction cache memory 31 are inhibited from being accessed, so the data processor fetches a new data block including the operation code at the head of a next instruction and non-head codes from main storage 5 through external buses 123 and 124. Therefore, the functions can easily be checked on the external buses 123 and 124.

35. 发明专利

JPH04284546A DATA PROCESSOR AND SYSTEM DEVELOPING DEVICE USING THE SAME 失效
公开(公告)号：JPH04284546A
公开(公告)日：1992-10-09
申请号：JP4934691
申请日：1991-03-14
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , KONDO YOSHIYUKI , HASHIMOTO KOJI
IPC分类号： G06F9/38 , G06F11/22 , G06F11/28 , G06F11/34
摘要： PURPOSE:To inform the outside of internal information by which an instruction in the course of execution in the microprocessor of an instruction pre-fetch system can be discriminated without increasing the number of pins or impairing a real time property. CONSTITUTION:In the microprocessor to fetch plural instructions at a time, a function to insert a special bus cycle for outputting the internal information of the processor to the outside at every execution of one instruction on the basis of a special bus cycle generation request signal SBR and an instruction execution end signal END, etc., is provided. A code for discriminating the corresponding executable instruction in a prefetched instruction group is outputted to byte codes BCO to BC3 during this special bus cycle. Since in the emulation of a system using the microprocessor of the instruction pre-fetch system, what instruction is executed can be easily known at the outside, correct emulation control can be attained, and simultaneously, the analysis of trace data is made easy, and debugging efficiency is improved.

36. 发明专利

JPH01314357A CACHE SYSTEM 失效
公开(公告)号：JPH01314357A
公开(公告)日：1989-12-19
申请号：JP14646888
申请日：1988-06-14
申请人： HITACHI LTD
发明人： UMINAGA MASAHIRO , AKITA HIDEHIKO , NOJIRI TORU , KAWASAKI IKUYA , INAYOSHI HIDEO
IPC分类号： G06F12/08 , G06F12/12
摘要： PURPOSE:To speed up access to a main memory by making the contents of a main memory location and a cache entry coincident with each other when the cache entry contents are expelled to the main memory. CONSTITUTION:Stacks 1, 2,... provided at a part of the main memory are first-in last-out types, which are controlled by two pointer registers. This invention features essentially that the majority of base pointers at the time of access is therefore access to the locations of stack head parts and further that locations above (lower address) the address of a location indicated by an SP are practically ineffective. Thus, the contents of the main memory location and cache entry are made coincident with each other when the cache entry contents are expelled to the main memory, so no complicate operation is required and the effective access to the main memory is speeded up.

37. 发明专利

JPH01263820A MICROPROCESSOR 失效
公开(公告)号：JPH01263820A
公开(公告)日：1989-10-20
申请号：JP9156188
申请日：1988-04-15
申请人： HITACHI LTD
发明人： ARAKAWA FUMIO , OKADA TETSUHIKO , KAWASAKI IKUYA
IPC分类号： G06F7/00
摘要： PURPOSE:To perform the processes in parallel with each other and to increase the processing speed in comparison with a computing element by putting 2 pieces of data on a bus at one time to carry out the AND and OR arithmetic operations via the bus and therefore using the computing element to another process. CONSTITUTION:An instruction prefetching part 2 transfers an instruction address to an address converting part 6 and at the same time transmits an instruction prefetching request. The part 6 converts a physical address into a logical address and sends it to an input/output control part 7. The part 7 prefetches an instruction to send it to the part 2 and the prefetched instruction is transferred to an instruction decoding part 1. The part 1 decodes said instruction and transfers the decoding information on the head address of a microinstruction, etc., to an arithmetic control part 3. The part 3 reads successively the microinstructions out of a microinstruction ROM 4 and latches them to a microinstruction register 5 to carry out the microinstruction.

38. 发明专利

JPH01156824A MICROPROCESSOR 失效
公开(公告)号：JPH01156824A
公开(公告)日：1989-06-20
申请号：JP31406387
申请日：1987-12-14
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： SAKAMURA TAKESHI , KAWASAKI IKUYA , HASEGAWA ATSUSHI , IWASAKI KAZUHIKO
IPC分类号： G06F7/00 , G06F9/30 , G06F9/305 , G06F9/318 , G06F9/32 , G06T11/40
摘要： PURPOSE:To secure the program flexibility and to facilitate the development of a program for the graphic processing, for example, by storing the information obtained by execution of a 1st instruction to an information holding means and controlling an instruction executing means based on said stored information when a 2nd instruction is carried out. CONSTITUTION:The type of an arithmetic operation is defined as one of operands. In other words, a desired arithmetic operation is carried out by an instruction that is added the operand information designating the type of the arithmetic operation to the outside or the inside of an operation designating part containing a common operation code showing an arithmetic operation (wide sense). Thus the contents of an operand are set previously to designate the type of the arithmetic operation based on the executing result of a certain instruction. Then the arithmetic operation is carried out based on the operand contents by the next instruction. Thus the type of the arithmetic operation can be changed into a dynamic one in a program. In such a way, the flexibility is secured to a program and the development of a program for graphic processing, for example, is facilitated.

39. 发明专利

JPS6472232A INFORMATION PROCESSOR WITH INVERSE DIRECTION STRING OPERATING INSTRUCTION 失效
公开(公告)号：JPS6472232A
公开(公告)日：1989-03-17
申请号：JP22833687
申请日：1987-09-14
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： UMINAGA MASAHIRO , KAWASAKI IKUYA , IWASAKI KAZUHIKO , HASEGAWA ATSUSHI , SAKAMURA TAKESHI , AKITA HIDEHIKO
IPC分类号： G06F9/30 , G06F17/30
摘要： PURPOSE:To obtain an information processor which is suited to process a string inversely in direction and to search the designated element that emerged last within the string. CONSTITUTION:An inverse direction string is obtained by reflecting a forward direction string on a mirror as shown in the diagram. In other words, the start address of the forward direction string points the left end of the string. While the start address of the inverse direction string points the right end of the string. In case a general-purpose register (GRO) points said start address, the address pointed by the GRO is moved right after an individual element is processed with the forward direction string. While the address pointed by the GRO is moved left before the individual element is processed with the inverse direction string. Thus it is possible to suitably process the string inversely or to suitably search the final element within the string by using the inverse direction string.

40. 发明专利

JPS63261449A DATA PROCESSOR 失效
公开(公告)号：JPS63261449A
公开(公告)日：1988-10-28
申请号：JP9518087
申请日：1987-04-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI ENG CO LTD
发明人： NAKAZAWA TAKUICHIROU , HASEGAWA ATSUSHI , KAWASAKI IKUYA , TATEZAKI JIYUNICHI , IWASAKI KAZUHIKO , HANAWA MAKOTO , MORINAGA SHIGEKI , KAJIWARA HISASHI , ASAI TAKESHI
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177
摘要： PURPOSE:To provide a coprocessor interface with generality and to improve the throughput of a system by forming a coprocessor specification area in a readable/writable area in a control register of a microprocessor. CONSTITUTION:A register (AOT) 19 capable of transferring a code included a coprocessor specification area PID in a status register 2a is provided and a 3-bit code inputted to the register 19 is supplied to an address output register 13 and can be outputted to 2nd and 4th bits in an external system address bus through an address bus 4. An identification (ID) code is set up in the PID area in said status register 2a by a temporary register (ECR) 18 connected to a bus BC in an execution unit 10 through a CCB bus 2c. Said register 2a can be receded to a stack area at the time of generating exceptions such as an incorrect instruction, an interruption, a bus error and a reset.

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