专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS63261449A DATA PROCESSOR 失效
公开(公告)号：JPS63261449A
公开(公告)日：1988-10-28
申请号：JP9518087
申请日：1987-04-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI ENG CO LTD
发明人： NAKAZAWA TAKUICHIROU , HASEGAWA ATSUSHI , KAWASAKI IKUYA , TATEZAKI JIYUNICHI , IWASAKI KAZUHIKO , HANAWA MAKOTO , MORINAGA SHIGEKI , KAJIWARA HISASHI , ASAI TAKESHI
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177
摘要： PURPOSE:To provide a coprocessor interface with generality and to improve the throughput of a system by forming a coprocessor specification area in a readable/writable area in a control register of a microprocessor. CONSTITUTION:A register (AOT) 19 capable of transferring a code included a coprocessor specification area PID in a status register 2a is provided and a 3-bit code inputted to the register 19 is supplied to an address output register 13 and can be outputted to 2nd and 4th bits in an external system address bus through an address bus 4. An identification (ID) code is set up in the PID area in said status register 2a by a temporary register (ECR) 18 connected to a bus BC in an execution unit 10 through a CCB bus 2c. Said register 2a can be receded to a stack area at the time of generating exceptions such as an incorrect instruction, an interruption, a bus error and a reset.

2. 发明专利

DE3852056D1 未知
公开(公告)号：DE3852056D1
公开(公告)日：1994-12-15
申请号：DE3852056
申请日：1988-04-15
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： MORINAGA SHIGEKI , NAKAGAWA NORIO , WATABE MITSURU , OHBA MAMORU , KIDA HIROYUKI , KAJIWARA HISASHI , ASAI TAKESHI , TATEZAKI JUNICHI
IPC分类号： G06F7/00 , G06F9/38 , G06F15/16 , G06F15/167
摘要： The interface portion of a coprocessor is provided with a FIFO (500) (First-in First-Out) and means for accepting instructions in succession. The pipeline control of the instructions becomes possible in this way, and protocol means (200) associated with a microprocessor is also provided.

3. 发明专利

DE68928376D1 未知
公开(公告)号：DE68928376D1
公开(公告)日：1997-11-13
申请号：DE68928376
申请日：1989-11-02
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NARITA MASAHISA , KAZIWARA HISASHI , ASAI TAKESHI , MORINAGA SHIGEKI , KIDA HIROYUKI , WATABE MITSURU , NAKAMIKAWA TETSUAKI , KAWASAKI SHUNPEI , TATEZAKI JUNICHI , NAKAGAWA NORIO , KASHIWAGI YUGO
IPC分类号： G06F7/52 , G06F7/483 , G06F7/535 , G06F7/552 , G06F7/57
摘要： An appts for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation. A multiplier, adder/subtractor and shifter each has a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.

4. 发明专利

DE3852056T2 未知
公开(公告)号：DE3852056T2
公开(公告)日：1995-03-16
申请号：DE3852056
申请日：1988-04-15
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： MORINAGA SHIGEKI , NAKAGAWA NORIO , WATABE MITSURU , OHBA MAMORU , KIDA HIROYUKI , KAJIWARA HISASHI , ASAI TAKESHI , TATEZAKI JUNICHI
IPC分类号： G06F7/00 , G06F9/38 , G06F15/16 , G06F15/167
摘要： The interface portion of a coprocessor is provided with a FIFO (500) (First-in First-Out) and means for accepting instructions in succession. The pipeline control of the instructions becomes possible in this way, and protocol means (200) associated with a microprocessor is also provided.

5. 发明专利

DE68928376T2 未知
公开(公告)号：DE68928376T2
公开(公告)日：1998-04-02
申请号：DE68928376
申请日：1989-11-02
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NARITA MASAHISA , KAZIWARA HISASHI , ASAI TAKESHI , MORINAGA SHIGEKI , KIDA HIROYUKI , WATABE MITSURU , NAKAMIKAWA TETSUAKI , KAWASAKI SHUNPEI , TATEZAKI JUNICHI , NAKAGAWA NORIO , KASHIWAGI YUGO
IPC分类号： G06F7/52 , G06F7/483 , G06F7/535 , G06F7/552 , G06F7/57
摘要： An appts for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation. A multiplier, adder/subtractor and shifter each has a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.

6. 发明专利

JPH02125331A DIVIDING AND MULTIPLYING SQUARE ROOT EXTRACTOR 失效
公开(公告)号：JPH02125331A
公开(公告)日：1990-05-14
申请号：JP27724288
申请日：1988-11-04
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NAKAMIGAWA TETSUAKI , KIDA HIROYUKI , WATABE MITSURU , MORINAGA SHIGEKI , KAJIWARA HISASHI , ASAI TAKESHI , NARITA MASAHISA
IPC分类号： G06F7/52 , G06F7/483 , G06F7/535 , G06F7/552
摘要： PURPOSE:To increase the approximating calculation speed in the Newton- Raphson's method by eliminating the difference in the number of transfer machine cycles from the output stage to the input stage of a multiplier between execution and non-execution of operation of the output of the multiplier in an adder/subtractor or a shifter. CONSTITUTION:A subtracting and shifting circuit is inserted between the output stage and the input stage of a multiplier 10, and the output of the multiplier 10 is directly inputted to a subtracting and shifting circuit 11, and the output result of this circuit 11 is inputted to the multiplier 10 through a bus 14 or a private local bus. That is, the multiplier 10 calculates a multiplication term in a recurrence formula, and the subtracting and shifting circuit 11 subtracts '2' or '3' from the output of the multiplier 10 and shifts the result as required, and the result is transferred to the multiplier 10 through the bus 14. Consequently, the recurrence formula is calculated. Thus, multiplication and division processings in the approximating calculation of the Newton-Raphson's method are continuously performed to increase the calculation speed.

7. 发明专利

JPH0282352A ARITHMETIC UNIT 失效
公开(公告)号：JPH0282352A
公开(公告)日：1990-03-22
申请号：JP23466388
申请日：1988-09-19
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： MORINAGA SHIGEKI , ASAI TAKESHI
IPC分类号： G06F17/16
摘要： PURPOSE:To reduce the arithmetic cycle by the combination of integration and addition by executing the multiplication of respective elements of a row vector and respective elements of a column vector with respective multipliers, and adding/subtracting respective multiplied values with an adder and a subtracter, respectively. CONSTITUTION:By a first multiplier 100, the multiplications of the first element of a row vector and the first element of a column vector is executed, by a second multiplier 101, the multiplications of the second element of a row vector and the second element of a column vector is executed, by a third multiplier 102, the multiplications of the third element of a row vector and the third element of a column vector is executed and by a fourth multiplier 103, the multiplication of the fourth element of a row vector and the fourth element of a column vector is executed. Respective integrated values are added and subtracted by a first adder-subtractor 108 and a second adder-subtractor 109. An arithmetic value by the first adder-subtractor 108 and the second adder-subtractor 109 is respectively added and subtracted through a third data extending unit 110 and a third shifter 111 with a third adder-subtractor 112. Thus, the arithmetic cycle by the combination of the multiplication and addition can be reduced.

8. 发明专利

JPH02137023A MULTIPLICATION/DIVISION SQUARE ROOT EXTRACTION ARITHMETIC UNIT AND BUS DEVICE 失效
公开(公告)号：JPH02137023A
公开(公告)日：1990-05-25
申请号：JP29024888
申请日：1988-11-18
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： NARITA MASAHISA , KAJIWARA HISASHI , ASAI TAKESHI , MORINAGA SHIGEKI , KIDA HIROYUKI , WATABE MITSURU , NAKAMIGAWA TETSUAKI
IPC分类号： G06F7/537 , G06F7/483 , G06F7/52 , G06F7/535 , G06F7/552
摘要： PURPOSE:To realize the continuous multiplication/division processes with use of the Newton-Raphson method by using both arithmetic units for small and large scales in addition to a multiplication device and applying the small and large scale operations when the arithmetic scale is smaller and larger than n bits respectively. CONSTITUTION:A multiplier 10 performs an (n X n)-bit multiplication process and outputs the 2n-bit result and then carries out plural multiplication processes in terms of a pipeline. Furthermore the multiplier 10 multiplies the contents of an n-bit multiplier source register 13 as well as the contents of an n-bit multiplier source register 12 and outputs these multiplication results to a subtraction shift circuit 11. The circuit 11 subtracts the output value of the multiplier 10 from 2 or 3 and at the same time performs the position matching of decimal points to output this matching result to a bus 14 of a 2n-bit constitution. A shift value variable shifter 15 shifts the data received from the bus 14 to the right and left by an optional number of bits and gives the shift result to an ALU 16 to apply a 2n-bit arithmetic process to the output of the shifter 15.

9. 发明专利

JPS63184135A ELEMENTARY FUNCTION ARITHMETIC UNIT 失效
公开(公告)号：JPS63184135A
公开(公告)日：1988-07-29
申请号：JP22565687
申请日：1987-09-09
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： KONDO EIKI , MORINAGA SHIGEKI , YAGINUMA TAKAO , ASAI TAKESHI
IPC分类号： G06F7/544 , G06F17/17
摘要： PURPOSE:To perform calculation with high accuracy with a comparatively few number of iteration, by performing iteractive calculation by assembling an error correction equation in a convergence calculating equation. CONSTITUTION:The initial values (a0, b0, and c0) of the argument and two constants of an elementary function to be found are inputted to computing elements 100, 101, and 103. Those computing elements perform n-times of sequen tial iterative calculation based on relative equations (ai+1=ai+ or -bi.deltai), (bi+1=bi+ or -ai.deltai), and (ci+1=ci+ or -cRi). The deltai is an arbitrary variation, and the cRi is the constant corresponding to the number of iteration, and they are stored in the memory 103 in advance. In a process of iteration, the value of the bi or the ci is inputted to a controller 104, and whether the calculation for (n+1)-times of the computing element are addition or subtraction is con trolled by a control signal (a) corresponding to the elementary function to be found. After n-times of iteration, arithmetic calculation of (dn=bn-m.an.cn) or (dn=cn+bn/an) is performed by a computing element 106, then, an elementary function value dn can be outputted.

10. 发明专利

JPS63259727A INTERFACE SYSTEM FOR COPROCESSOR 失效
公开(公告)号：JPS63259727A
公开(公告)日：1988-10-26
申请号：JP9309887
申请日：1987-04-17
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： MORINAGA SHIGEKI , NAKAGAWA NORIO , WATABE MITSURU , OBA MAMORU , KIDA HIROYUKI , KAJIWARA HISASHI , ASAI TAKESHI , TATEZAKI JIYUNICHI
IPC分类号： G06F7/00 , G06F9/38 , G06F15/16 , G06F15/167
摘要： PURPOSE:To speed up operation speed by providing an FIFO (First In First Out) in the interface part of a coprocessor, and making the acceptance of statement in the coprocessor into a pipe line. CONSTITUTION:An FPU (Floating point Processing Unit) 101 is provided with a FIFO to fetch the DATA of a data bus 105 related to a command or an operand, and the FPU101 operates on receiving signals AT2-AT0 to indicate the kind of an access from a CPU100 and execute a coprocessor protocol by returning the signals CPST2-CPST0 to the CPU100. Thus, since a command pipe line is possible, the overhead of the interface in the floating point operation can be reduced, and the operation speed can be speeded up.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式