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31. 发明专利

JPH06181236A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH06181236A
公开(公告)日：1994-06-28
申请号：JP33434292
申请日：1992-12-15
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： NISHIDA TAKAFUMI , ICHIHARA SEIICHI , NISHI KUNIHIKO , SHIMOISHI TOMOAKI , KAWAKUBO HIROSHI , NAKAMURA TOSHIO
IPC分类号： H01L21/60 , H01L23/29
摘要： PURPOSE:To reduce the thermal resistance of tape carrier packages and to increase the manufacture yield of the tape carrier packages. CONSTITUTION:The title semiconductor integrated circuit device is a tape carrier package 10 made by joining a metal plate 7 on the rear side of a semiconductor chip 4, and sealing only the front side with resin 8. To manufacture this tape carrier package 10, a semiconductor chip 4 with a metal plate 7 joined to the rear side beforehand is fitted to a molding die, and only the front side of the semiconductor chip 4 is sealed with resin by transfer molding.

32. 发明专利

JP2001332645A SEMICONDUCTOR DEVICE AND IS MANUFACTURING METHOD 失效
公开(公告)号：JP2001332645A
公开(公告)日：2001-11-30
申请号：JP2000148322
申请日：2000-05-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HAGIWARA YASUHISA , ICHIHARA SEIICHI , SUZUKI HIDENORI , MIYAKI YOSHINORI
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To improve reliability in a semiconductor device where a tape substrate is used. SOLUTION: The device consists of a tape substrate 2 provided with a plurality of leads 2a connected to a pad of a semiconductor chip 1 corresponding thereto, a plurality of solder balls which are disposed in an outer circumference of the semiconductor chip 1 and fixed to the end of an external terminal fixing surface 2b of the tape substrate 2, and a frame-like reinforcement member 4 provided to an outer circumferential end of a back side of the tape substrate 2. A dummy lead 2e crossing an inner end 4a of the reinforcement member 4 is provided to a vacant region 2g at one or both sides or the lead 2a crossing an inner end 4a of the frame-like reinforcement member 4. As a result, stress applied to a place corresponding to an area near an inner end of he reinforcement member 4 of a lead group disposed at high density can be proved by scattering in each lead 2a and the dummy lead 2e without concentrating to the lead 2a at an outermost side of a lead group.

33. 发明专利

JP2001185585A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001185585A
公开(公告)日：2001-07-06
申请号：JP36716199
申请日：1999-12-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MIYAKI YOSHINORI , HAGIWARA YASUHISA , ICHIHARA SEIICHI , NAKAMURA TOSHIO , SUZUKI HIDENORI
IPC分类号： H01L23/12 , H01L21/60 , H01L23/495 , H01L23/498
摘要： PROBLEM TO BE SOLVED: To improve connecting reliability in an external terminal of a semiconductor device used for a tape substrate. SOLUTION: The semiconductor device comprises a tape substrate provided with a plurality of leads 2a supporting a semiconductor chip 1 and connecting to pads 1a of the semiconductor chips 1, and dummy lead 2e at a corner so as to dispose the lead 2a in symmetry with a diagonal line 5; a gold bump connecting a pad 1a of the semiconductor device 1 with the lead 2a of the tape substrate 2; a frame reinforcing member formed on the back of the tape substrate 2; and a plurality of solder balls fixed on an external terminal fixing surface 2b of the tape substrate 2, and disposed on the outer periphery of the semiconductor chip 1. A stress acting on the corner of the tape substrate 2 is disposed to all of the corner by the dummy lead 2e.

34. 发明专利

JPH1140745A SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCORPORATING THE SAME 失效
公开(公告)号：JPH1140745A
公开(公告)日：1999-02-12
申请号：JP19228297
申请日：1997-07-17
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： KAWAKUBO HIROSHI , KIMOTO RYOSUKE , ICHIHARA SEIICHI , NAKAMURA TOSHIO
IPC分类号： H01L25/18 , H01L23/50 , H01L25/10 , H01L25/11 , H05K1/18 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To reduce the size of a stack mounting portion. SOLUTION: A plurality of semiconductor devices (TCP-type stack-mounting semiconductor devices) whose leads 5u and 5d are projected side by side from side surfaces of packages 4, 4d and 4u, and which are to be mounted on a wiring board so as to be superposed, are such that their leads have the same projecting length, and at least mounting ends of the leads 5u and 5d of one of the semiconductor devices are arranged side by side with mounting ends 6u and 6d of the leads of the other semiconductor device, so as to be superposed one upon another. The packages 4, 4u and 4d of the plurality of semiconductor devices have the same size. The semiconductor devices are constituted of memory semiconductor devices. The stack-mounting semiconductor devices are an upper TCP 3 and a lower TCP 2.

35. 发明专利

JPH10303255A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH10303255A
公开(公告)日：1998-11-13
申请号：JP10998297
申请日：1997-04-28
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK , HITACHI DEVICE ENG
发明人： OKAMURA KAZUHIRO , ICHIHARA SEIICHI , MORI HIROYUKI , AKIMOTO KOJI , KIMURA MAKOTO
IPC分类号： H01L21/60 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To control the sneaking of resin to the backside of a tape carrier sealing resin and to realize slim TCP(tape carrier package). SOLUTION: A device is constituted of a tape carrier 2 which is provided with backside 2c that are overlapped and arranged with the outer peripheral part of a main face 1b of a semiconductor chip 1 and is provided with auxiliary opening parts 2e promoting the infiltrating of sealing resin at the time of sealing resin and of a resin sealing part 6 which resin-seals a joint part 4 of the electrode of the semiconductor chip 1 and the lead 2a of the tape carrier 2 and the peripheral part 5. Each auxiliary opening part 2e is provided for both end parts of a long device hole 2d where the leads 2a of the tape carrier 2 are arranged. Thus, the sneaking of resin from the main face 2b of the tape carrier 2 to a backside 2c in sealing resin is promoted.

36. 发明专利

JPH0778845A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0778845A
公开(公告)日：1995-03-20
申请号：JP16092193
申请日：1993-06-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： YAMAZAKI KAZUO , ICHIHARA SEIICHI
IPC分类号： H01L21/60 , H01L23/12 , H05K3/34
摘要： PURPOSE:To obviate the short-circuit defects in the packaging time of semiconductor device thereby enhancing the yield of an electronic device by removing at least a part of the second wiring layer on the periphery of an outer lead hole. CONSTITUTION:A Cu conductor layer and an insulating tape 2 formed on the rear surface are patterned by photolithographic and etching technologies so as to make a device hole and an outer lead hole. At this time, the second wiring layer 4 is removed on the periphery of an outer lead hole. Thus, even if an outer lead 3c is bent on the insulating tape 2 side near the terminal end of the insulating tape 2 to be soldered onto a printed substrate 6, the solder 7 for packaging the outer lead 3c does not come into contact with the second conductor layer 4. Accordingly, the outer lead 3c is not short-circuited with the second conductor layer 4 thereby enabling the short-circuit defects in the packaging time to be obviated further enhancing the yield of an electrode device.

37. 发明专利

JPH01215031A RESIN-SEALED PIN GRID ARRAY TYPE SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JPH01215031A
公开(公告)日：1989-08-29
申请号：JP3945888
申请日：1988-02-24
申请人： HITACHI LTD , HITACHI MICROCUMPOTER ENG
发明人： ICHIHARA SEIICHI , TONO TOMOKO , OKANO KUMIKO , HAGIWARA YASUHISA
IPC分类号： H01L21/60
摘要： PURPOSE:To decrease the number of processes, and to reduce cost by incorporating a semiconductor pellet into a carrier tape while drooping ly providing the tape with a pin, introducing an assembly to a molding die and transfer-molding and resin-sealing the assembly. CONSTITUTION:A conductor foil is stuck onto a carrier tape 2, a conductor wiring 3 is formed through etching working, and through-holes for droopingly providing pins 4 for external connection are bored to the conductor wiring 3 and the carrier tape 2. Conductive resin adhesives 5 are applied to a pellet fixing section on the carrier tape 2 and the joining sections of the conductor wiring 3 and the pins 4 for external connection, and a pellet 6 is fixed onto the surface of the carrier tape 2 while the pins 4 for external connection are inserted in the downward direction in the through-holes, and fastened to the conductor wiring 3. The pellet 6 and the conductor wiring 3 are connected electrically by wires 7 for connectors, and an assembly is admitted into a molding die, transfer molded, and resin-sealed by a resin seal section 8.

38. 发明专利

JPS59188155A Semiconductor pellet mount 失效
标题翻译： SEMICONDUCTOR PELLET MOUNT
公开(公告)号：JPS59188155A
公开(公告)日：1984-10-25
申请号：JP6088783
申请日：1983-04-08
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： ICHIHARA SEIICHI , KAWANOBE TOORU , OOTSUKA KENICHI , MIYAMOTO KEIJI , INABA KICHIJI , KIMOTO RIYOUSUKE
IPC分类号： H01L21/60 , H05K3/30 , H05K3/34
CPC分类号： H01L24/81 , H01L2224/14505 , H01L2224/81136 , H01L2224/81139 , H01L2224/81801 , H01L2924/014 , H05K3/303 , H05K3/3436 , H05K3/3452
摘要： PURPOSE:To enable to readily control the connecting shape of a solder, to provide high reliability and high workability, and to suppress the increase in the manufacturing steps by forming an isolator solder height not moistened to an insulating substrate to a semiconductor pellet. CONSTITUTION:A mounting surface of a semiconductor pellet 1 is composed to be electrically independent from a connecting electrode 2 of an independent electrode 18, and a connecting solder height 6 and an isolating solder height 19 are formd. A connecting electrode 5 and a hydrophobic film 17 are formed on an insulating substrate 4. The film 17 is formed by printing a metal material such as titanium, and a solder height 7 is formed on the electrode 5. A semiconductor pellet 1 and the substrate 4 are positioned, and heated to form a connecting solder 3 and an isolating solder 16. Since the solder 16 tends to maintain spherical shape of the prescribed size, the solder 3 and the connecting height as well as the connecting shape are controlled, and formed in a columnar or swelled shape.
摘要翻译：目的：为了能够容易地控制焊料的连接形状，提供高可靠性和高加工性，并且通过将未被浸透到绝缘基板的隔离器焊料高度形成为半导体芯片来抑制制造步骤的增加。构成：将半导体芯片1的安装面与独立电极18的连接电极2电气独立，形成连接焊料高度6和隔离焊料高度19。连接电极5和疏水膜17形成在绝缘基板4上。薄膜17通过印刷诸如钛的金属材料形成，并且在电极5上形成焊料高度7.半导体芯片1和基板 4被定位并被加热以形成连接焊料3和隔离焊料16.由于焊料16趋于保持规定尺寸的球形，焊料3和连接高度以及连接形状被控制并形成呈柱形或膨胀形状。

39. 发明专利

JP2003023033A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003023033A
公开(公告)日：2003-01-24
申请号：JP2001207653
申请日：2001-07-09
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NAKAMURA TOSHIO , ICHIHARA SEIICHI , SHIMOISHI TOMOAKI , SASAKI MASAKO , KAWAKUBO HIROSHI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a package without warpages irrespective of the arrangement of an electrode pad.
SOLUTION: The bumps 15 of a pellet 10 are mechanically and electrically connected to a carrier tape where a plurality of inner leads 24 are arranged in a tape body 21 by a resin-sealing object 32 constituted of an anisotropic conductive adhesive. A flat reinforcement plate 27 is fixed to the second face of the pellet loading part 23 of the tape body 21. The inner leads 24 are laid out in the tape body 21 without a device hole. Since the warpage of the pellet loading part can be prevented, the inner leads and the pads of the pellet can uniformly and electrically be connected via the bump. The degree of freedom on the pull of the inner lead to the pellet loading part can be improved by laying out the inner lead to the pellet loading part without device holes. Since the connection part of the pellet and the inner lead can be resin-sealed by anisotropic conductive adhesive, the forming process of the resin sealing object can be omitted.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：无论电极垫的布置如何，都能提供一种不受扭曲的包装。解决方案：颗粒10的凸起15通过由各向异性导电粘合剂构成的树脂密封对象32机械地和电连接到载带，其中多个内引线24布置在带体21中。平板加强板27固定到带体21的颗粒装载部分23的第二面上。内引线24布置在带体21中而没有装置孔。由于能够防止粒料负载部的翘曲，因此能够使内部引线和芯片的焊盘通过凸块均匀地电连接。可以通过将内部引线布置到没有装置孔的颗粒装载部分来提高内部引线到颗粒装载部分的拉动的自由度。由于颗粒的连接部分和内部引线可以通过各向异性导电粘合剂树脂密封，所以可以省略树脂密封体的形成过程。

40. 发明专利

JP2002158309A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002158309A
公开(公告)日：2002-05-31
申请号：JP2000353065
申请日：2000-11-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MIYAKI YOSHINORI , ICHIHARA SEIICHI
IPC分类号： H01L23/12 , H01L21/60 , H01L25/04 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein work of a substrate which uses tape base substance is standardized, failure due to bending of a lead is reduced, and a product of a narrow pad pitch can be realized. SOLUTION: A semiconductor device of a T-TFBGA package using a COF structure consists of a substrate 1 wherein a wiring layer is formed on the tape base substance 5, a chip 2 mounted on a surface of the substrate 1, sealing agent 3 for sealing a connection part between the chip 2 and the substrate 1, external terminals 4 mounted on the back of the substrate 1, etc. In a package structure, a wiring pattern 6 on the tape base substance 5 of the substrate 1 and the chip 2 mounted on the substrate 1, and the external terminals 4 of the package are positioned on the opposite sides interposing the tape base substance 5 of the substrate 1. As a result, device holes of the tape base substance 5 are unnecessary, and a lead part 7 of the substrate 1 which is connected with an electrode 11 of the chip 2 by using a wiring is fixed on the tape base substance 5.

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