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31. 发明专利

JPH0786601A POLYCRYSTALLINE SILICON MOS TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0786601A
公开(公告)日：1995-03-31
申请号：JP22544193
申请日：1993-09-10
申请人： HITACHI LTD
发明人： KOBAYASHI TAKASHI , IIJIMA SHINPEI , SHIGENIWA MASAHIRO , OKURA OSAMU , WADA YASUO , HASHIMOTO KOJI
IPC分类号： H01L27/11 , H01L21/336 , H01L21/8244 , H01L29/78 , H01L29/786
摘要： PURPOSE:To reduce a grain boundary, and to improve characteristics by positively controlling the position of the grain boundary by growing a crystal toward a current path section from a diffusion layer section. CONSTITUTION:A thermal oxide film 102 is formed onto an Si substrate 101, and an amorphous Si film 103 is deposited while introducing phosphorus. An amorphous Si film 104 containing no impurity is deposited, and used as the current path of a MOS transistor. Crystal nuclei are formed first in the amorphous Si pattern 103 (105) and an Si film containing no impurity is crystallized (106) through heat treatment. There is only one grain boundary 107 in the amorphous Si film containing no impurity when heat treatment is completed. Phosphorus in the Si film 105 is diffused up to the surface of the Si film 106 comprising no impurity at the same time as crystallization. An amorphous Si film 109 is thermally treated and used as electrode, and a metallic film 111 is deposited and employed as an extraction electrode.

32. 发明专利

JPH06274341A MICROCOMPUTER 失效
公开(公告)号：JPH06274341A
公开(公告)日：1994-09-30
申请号：JP8273693
申请日：1993-03-17
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： WATASE HIROSHI , KUBO MITSUYUKI , MIURA MASAHARU , KUROIWA TAKASHI , NEGISHI SEIICHI , TAKAKUBO KATSUHARU , HASHIMOTO KOJI
IPC分类号： G06F9/38
摘要： PURPOSE:To provide a technique for relieving the decrease of instruction look- ahead efficiency, which transitionally occurs when a program is branched. CONSTITUTION:A branch destination instruction part 7 which can hold the execution history of a branch instruction, a branch destination address part 8, an address association part 6 monitoring an instruction look-ahead address and a pre-fetch address generation part 2 generating an address for next look- ahead based on execution history when the instruction look-ahead address hits the execution history of the branch instruction are Provided. The decrease of instruction look-ahead efficiency is relieved by predicting branching.

33. 发明专利

JPH06224392A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06224392A
公开(公告)日：1994-08-12
申请号：JP978093
申请日：1993-01-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASHIMOTO KOJI , MINE TOSHIYUKI , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , SHIMIZU AKIHIRO , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L27/11 , H01L21/8244 , H01L29/78 , H01L29/786 , H01L29/784
摘要： PURPOSE:To provide a semiconductor device by using a double-layer insulator of SiO2 and Si3N4 so as to solve such problems as the decrease in yield due to an increase in defect density or the adverse effects of threshold fluctuations on reliability. CONSTITUTION:A semiconductor device has a structure in which an electrode is provided on each side of an insulating laminate including an SiO2 film 105 and an Si3N4 film 104. When a positive voltage is applied to the electrode in contact with the SiO2 film 105, negative charge appears in the laminated insulator. Such a double-layer insulating laminate of SiO2 105 and Si3N4 104 is used to decrease the thickness of the gate oxide of polysilicon p-MOS transistors in memory cells. The insulating laminate is thinner than 15nm in terms of the thickness of oxide. The SiO2 105 is on the gate side while Si3N4 104 is on the channel side. The SiO2 105 is thicker than the Si3N4 104. The double-layer insulating laminate has a sufficient dielectric breakdown strength and a good aging breakdown characteristic.

34. 发明专利

JPH06208796A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06208796A
公开(公告)日：1994-07-26
申请号：JP31772293
申请日：1993-12-17
申请人： HITACHI LTD
发明人： MATSUNO KATSUMI , NAKAGOME YOSHINOBU , TAKEUCHI MIKI , OJI YUZURU , AOKI MASAKAZU , HASHIMOTO KOJI , WATABE TAKAO
IPC分类号： G11C11/22 , G11C14/00 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/786 , H01L29/788 , H01L29/792 , H01L29/784
摘要： PURPOSE:To obtain a low noise, low power consumption, high integration non- volatile semiconductor memory which can retain information stably by employing a ferroelectric. CONSTITUTION:When the operation is ended, a selection transistor is turned OFF after equalizing the potentials, of data line and a plate electrode. At the time of waiting, potential at an information accumulating node is sustained close to the plate potential through the leak of the selection transistor and a ferroelectric capacitor. At the time of reading, data line isolation switches CSWa1,... are interrupted upon finish of amplification through sense amplifiers SAa1,... and a memory cell array is returned to waiting state. Consequently, information can be retained stably with low power consumption even if the plate potential is constant. Since the leak characteristic request of the selection transistor and ferroelectric film is not strict, memories can be fabricated easily with high yield. Furthermore, a memory requiring no formation of well can be obtained by employing a thin film transistor as the selection transistor.

35. 发明专利

JPH05136402A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05136402A
公开(公告)日：1993-06-01
申请号：JP30022191
申请日：1991-11-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA HIROSHI , SHIMIZU AKIHIRO , HASEGAWA NORIO , MORIMOTO TADAO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , OOKI NAGATOSHI
IPC分类号： H01L21/265 , H01L21/266 , H01L21/28 , H01L29/78
摘要： PURPOSE:To enable micromachining forming a second mask narrower than a first mask patterned by photolithography. CONSTITUTION:A silicon substrate 1 is spread with a gate oxide film 2, a polycrystalline silicon film 3, an oxide film 4, and a polycrystalline silicon film 5 serving as a second mask material up t about 50nm; and then, with lower layer and intermediate layer resist films 6,7 and formed into an upper layer resist film pattern 8 by lithography. Next, it is transferred onto the intermediate resist film 7 to form a pattern 7' and likewise a pattern 6', and the intermediate layer resist pattern 7' is removed: with the lower resist pattern 6' used as a mask to the polycrystalline film 5 is isotropically over-etched by dry-etching to form a polycrystalline silicon pattern 5' made narrower than the pattern 6'. The pattern 6' is removed and used as a mask etch the oxide film 4 anisotropically by dryetching, so that a microsize of 0.1mum or less can be controlled.

36. 发明专利

JPH0590588A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0590588A
公开(公告)日：1993-04-09
申请号：JP4362191
申请日：1991-03-08
申请人： HITACHI LTD
发明人： YAMANAKA TOSHIAKI , HASHIMOTO KOJI , HASHIMOTO NAOTAKA , TAKEDA EIJI
IPC分类号： H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786
摘要： PURPOSE:To provide a semiconductor device and a semiconductor memory device having an insulation gate type field effect transistor which uses a polycrystal silicon film which is capable of minimizing leak current and controlling threshold voltage. CONSTITUTION:A channel region of a first conductivity type insulation gate type field effect transistor formed in a polycrystalline silicon film is divided into a first channel region 3c at a part contacting with a drain region 3b and a second channel region 3d at other parts. It is so arranged that the second channel region 3d may contain second conductive type impurities or first conductivity type impurities whose concentration is higher than that of the first channel region 3c.

37. 发明专利

JPH04287345A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04287345A
公开(公告)日：1992-10-12
申请号：JP5218891
申请日：1991-03-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASHIMOTO NAOTAKA , YAMANAKA TOSHIAKI , HASHIMOTO KOJI , SHIMIZU AKIHIRO
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PURPOSE:To obtain a fine element isolation structure and its manufacturing method excellent in the high level of integration. CONSTITUTION:The lower part of an element isolation region is a high concentration impurity layer 2 having the same conductivity type as a semiconductor substrate. The bottom surface is in contact with the substrate 1. On the side surface, a selective epitaxial layer 5 turning to an element region is formed via a thin insulating film 3. On the upper surface, a nitride film 4 is formed via a thin oxide film. A high concentration impurity layer 6 having the same conductivity type as the substrate 1 is formed inside the element region and the element isolation region. According to this invention, by forming a nitride film on the upper surface of a field insulating film, the exfoliation of the field insulating film can be prevented when connection holes are opened. Since the effective element isolation length is not damaged, fine element isolation is realized. Further, by thinning the field insulating film, the electric potential distribution is restricted within a shallow region, and the potential on the element region end can be restrained from increasing, so that the leak current can be prevented.

38. 发明专利

JPH04284546A DATA PROCESSOR AND SYSTEM DEVELOPING DEVICE USING THE SAME 失效
公开(公告)号：JPH04284546A
公开(公告)日：1992-10-09
申请号：JP4934691
申请日：1991-03-14
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , KONDO YOSHIYUKI , HASHIMOTO KOJI
IPC分类号： G06F9/38 , G06F11/22 , G06F11/28 , G06F11/34
摘要： PURPOSE:To inform the outside of internal information by which an instruction in the course of execution in the microprocessor of an instruction pre-fetch system can be discriminated without increasing the number of pins or impairing a real time property. CONSTITUTION:In the microprocessor to fetch plural instructions at a time, a function to insert a special bus cycle for outputting the internal information of the processor to the outside at every execution of one instruction on the basis of a special bus cycle generation request signal SBR and an instruction execution end signal END, etc., is provided. A code for discriminating the corresponding executable instruction in a prefetched instruction group is outputted to byte codes BCO to BC3 during this special bus cycle. Since in the emulation of a system using the microprocessor of the instruction pre-fetch system, what instruction is executed can be easily known at the outside, correct emulation control can be attained, and simultaneously, the analysis of trace data is made easy, and debugging efficiency is improved.

39. 发明专利

JPH04162668A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04162668A
公开(公告)日：1992-06-08
申请号：JP28705890
申请日：1990-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMANAKA TOSHIAKI , HASEGAWA NORIO , TANAKA TOSHIHIKO , HASHIMOTO KOJI , ISHIBASHI KOICHIRO , HASHIMOTO NAOTAKA , SHIMIZU AKIHIRO , SUGAWARA YASUHIRO , KURE TOKUO , IIJIMA SHINPEI , NISHIDA TAKASHI , TAKEDA EIJI
IPC分类号： G03F1/29 , G03F1/30 , G03F1/68 , H01L21/027 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To enable wiring resistance to be reduced and a memory cell area to be reduced by placing a conductive film which fixes a source potential of a MOS transistor for drive at a reference potential on an upper part than the MOS transistor after covering an entire surface of the memory cell. CONSTITUTION:MOS transistors for driving an n channel T1 and T2 and MOS transistors T3 and T4 for transferring the n channel are formed within a p-type well 24 which is formed within an n-type silicon substrate 23. A connection hole 14c is opened on a high-concentration n-type impurities region 12c which becomes a common source of the MOS transistors T1 and T2. A second-layer conductive film 15c for fixing a source potential of all MOS transistors for drive within the memory cell is connected to the region 12c through the connection hole 14c, thus enabling a memory cell area to be reduced while reducing resistance of wiring resistor of the conductive film for fixing the source potential to the reference potential.

40. 发明专利

JPH01268064A FORMATION OF POLYCRYSTALLINE SILICON THIN FILM 失效
公开(公告)号：JPH01268064A
公开(公告)日：1989-10-25
申请号：JP9556488
申请日：1988-04-20
申请人： HITACHI LTD
发明人： HASHIMOTO KOJI , KAWAMOTO YOSHIFUMI , KOBAYASHI TAKASHI
IPC分类号： H01L21/205 , H01L21/336 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/78 , H01L29/786
摘要： PURPOSE:To make it possible to manufacture a polycrystalline Si MOS type field-effect transistor characterized by a small OFF current, a small absolute value of threshold voltage and a large operating current, by using disilane or trisilane as a reacting gas, performing deposition in an amorphous state at a specified temperature, performing a heat treatment and polycrystallization. CONSTITUTION:Decomposition is performed at a temperature of 550 deg.C or less by using disilane or trisilane as a reacting gas, and deposition is performed under an amorphous state. Heat treatment is performed at a temperature higher than the deposition temperature, and a polycrystalline state is obtained. For example, an amorphous Si film 13 is deposited on an SiO2 film 12 on a P-type Si substrate 11 by an LPCVD method by using Si2H6 gas as a reacting gas at a temperature of 520 deg.C. The film is patterned in an island shape. Thereafter, an SiO2 film 14 is deposited. Heat treatment is performed at 900 deg.C, and a gate oxide film is obtained. Then, P ions are implanted in the polycrystalline Si 13. A polycrystalline Si film is deposited by using SiH4 as a reacting gas, and a gate electrode 15 is formed. Then, an SiO2 film is formed by heat treatment. BF2 ions are implanted, and P-type high concentration impurity regions for a source, a drain and a gate are formed.

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