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31. 发明专利

JPS60167525A GENERATING CIRCUIT OF INTERNAL CLOCK 失效
公开(公告)号：JPS60167525A
公开(公告)日：1985-08-30
申请号：JP2176884
申请日：1984-02-10
申请人： HITACHI LTD
发明人： KANEKO KENJI , TAKAGI KATSUAKI , MATSUURA TATSUJI , HAGIWARA YOSHIMUNE
IPC分类号： H03L7/18 , G06F1/08 , G11C11/407 , H03K5/00 , H03L7/107 , H03L7/183
摘要： PURPOSE:To produce an internal clock signal having a higher frequency than an external clock signal and also synchronous with said external clock signal, by providing a PLL circuit to an internal clock circuit. CONSTITUTION:A reference clock signal R (frequency fR) is applied to a frequency multiplying circuit 12 of an integrated circuit 11 from outside or an oscillation circuit OSC13. Then a signal S of a high frequency nfR (n: an integer) which is synchronous with the signal R is produced. A frequency multiplying circuit A consists of a PLL circuit (shown in a figure). The input signals M and N of frequency dividing circuits CNTR1 and 2 function to set the number of divisions respectively. With this internal clock generating circuit, a signal RM of a frequency of 1/M compared with the signal R is equal to a signal SN of a frequency of 1/N compared with the output signal S (frequency fS) of a VCO25 together with phases synchronous with each other. As a result, a signal S of the frequency fS equal to N.fR/M is obtained. Here fS>fR is satisfied with N/M>1. Furthermore the specific constant of an LPF24 is set variable to ensure an action corresponding to a wide range of external clock frequencies.

32. 发明专利

JPS6060765A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6060765A
公开(公告)日：1985-04-08
申请号：JP16817183
申请日：1983-09-14
申请人： HITACHI LTD
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/76 , H01L21/8249 , H01L27/06 , H01L29/78
摘要： PURPOSE:To reduce parasitic capacitance and parasitic resistance, and to enable operation at high speed by thinning an oxide film on a section as a contact for a source of a drain in an MOS integrated circuit. CONSTITUTION:An oxide film 5 and a non-oxidizable film 6 are formed on a substrate 100, and oxidized while leaving the film 6 in a desired section to shape a thick oxide film 7. A polycrystalline silicon layer 15 is formed to an opening section 12 shaped by etching the film 6, and impurity ions are implanted to form a source region 18 and a drain region 19. An oxide film 20 is formed through oxidation, the non-oxidizable film 6 is removed and the thin oxide film 5 is also removed, and contact holes 24, 25 for a source and a drain are shaped. Lastly, electrodes 27, 28 are formed.

33. 发明专利

JPS6012757A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6012757A
公开(公告)日：1985-01-23
申请号：JP11834583
申请日：1983-07-01
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/8226 , H01L27/082 , H03K19/018 , H03K19/091 , H01L27/08 , H03K19/00
摘要： PURPOSE:To make the operation stable and highly accurate by a method wherein the collector-base coupling or the drain-gate coupling of transistors determining constant current is connected to the collector or drain of the other transistor pair for constant current generation having polarity different from that of said pair, in the IC with an I L circuit incorporated in the emitter or source side of the transistor pair constituting a constant current circuit. CONSTITUTION:The other pair of constant current transistors Q3 and Q4 having the polarity inverse to that of the following pair are connected to the pair of constant current transistors Q1 and Q2 with the I L circuit incorporated, and the collector of Q3 is connected to that of Q1. The output current of Q2 is determined by the transistor Q4 and a resistor RB1 in such a manner. This circuit allows the potential of a point A to vary with the action of the circuit 10. Even when the potential of a point B varies according to it, the variation of the value of current flowing through Q1 and Q2 becomes completely eliminated because of the high impedance of Q3 on the collector side from the point B.

34. 发明专利

JPS5979566A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5979566A
公开(公告)日：1984-05-08
申请号：JP18904982
申请日：1982-10-29
申请人： Hitachi Ltd
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L29/417 , H01L29/73
CPC分类号： H01L29/41708
摘要： PURPOSE:To narrow the interval between emitter, base electrode windows, to reduce the area, and to enhance the frequency characteristic of a semiconductor device by a method wherein the base terminals of the vertical transistor are led out according to poly-Si layers. CONSTITUTION:An N type epitaxial layer 52 on a P type Si substrate 50 buried with an N type layer 51 is isolated by P type layers 53 and field oxide films 54, and a P type layer 2 is provided. An SiO2 film 60 and an Si3N4 film 61 are accumulated, windows are opened, N type poly-Si layers 90 added with P are provided selectively, and the surfaces thereof are covered with SiO2 film 55. Windows are opened in the films 60, 61, P ions are implanted covering the collector electrode windows with a resist to provide an N type base 3, then a P type emitter 4 and P type collector lead out layers 10 are provided, and a heat treatment is performed to connect base lead out layers 5 to the N type base 3. Electrodes 6, 7 are equipped finally. According to this construction, the distances between the emitter electrode 6 and the base electrodes 7 of the vertical transistor can be made to 2mum or less to be reduced to 1/4 of usual, the element can be formed in a small type, junction capacity reduced, and the frequency characteristic is improved.
摘要翻译：目的：通过以垂直晶体管的基极端子根据多晶Si层引出的方法，缩小发射极，基极窗口之间的间隔，减小面积，并提高半导体器件的频率特性。构成：通过P型层53和场氧化膜54隔离在N +型层51上埋设的P型Si衬底50上的N型外延层52，并提供P型层2。堆积SiO 2膜60和Si 3 N 4膜61，打开窗口，选择性地提供添加有P的N +型多晶硅层90，并且其表面被SiO 2膜55覆盖。窗口在膜中打开 60,61，用抗蚀剂注入覆盖集电极窗口的P离子以提供N型基体3，然后提供P +型发射体4和P +型集电极引出层10，并且加热执行处理以将基底引出层5连接到N型基底3.电极6,7最终装备。根据这种结构，垂直晶体管的发射极电极6和基极电极7之间的距离可以为2μm或更小，以减小到通常的1/4，元件可以形成为小型的结电容降低，频率特性提高。

35. 发明专利

JPS5947843A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：JPS5947843A
公开(公告)日：1984-03-17
申请号：JP15661482
申请日：1982-09-10
申请人： Hitachi Ltd
发明人： KOJIMA NOBORU , SHIBATA AKIRA , AZEYANAGI TOMOMITSU , OKABE TAKAHIRO , KANEKO KENJI
IPC分类号： H03K19/091
CPC分类号： H03K19/091
摘要： PURPOSE:To prevent malfunction, by constituting I L circuit blocks in stack structure so that the number of interfaces leading a signal from the upper to the lower stages is decreased less than the number of interfaces leading the signal from the lower to the upper stages. CONSTITUTION:The stack of the I L circuit blocks 41, 42 of a bypolar logical circuit is constituted by connecting the blocks from the upper to the lower stages in cascade. The size of the I L circuit blocks 41, 42 represents the number of I L gate circuits included in the blocks and the number of the gate circuits of the I L circuit block 41 of the upper stage is more than that of the lower stage. Further, when the number driving the I L high speed I L gate circuits with the low speed I L gate circuits is less, the number B of the interfaces from the upper to the lower stages is less than the number A of interfaces from the lower to the upper stages.
摘要翻译：目的：为了防止故障，通过构成堆叠结构中的I <2> L电路块，从而使从上到下的信号的接口数量减少到小于将信号从较低层引导到上阶段构成：由极性逻辑电路的I 2 L电路块41,42的堆叠通过级联连接从上层到下级的块来构成。 I 2 L电路块41,42的大小表示包括在块中的I 2 L门电路的数量和上级的I 2 L电路块41的门电路的数量超过了下一阶段。此外，当驱动具有低速I 2 L门电路的I 2 L高速I 2 L门电路的数量较少时，从上到下级的接口的数量B较少比从下到上的接口数量A。

36. 发明专利

JPS5930327A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS5930327A
公开(公告)日：1984-02-17
申请号：JP14151582
申请日：1982-08-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KANEKO KENJI , MATSUMOTO KEIZOU , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/8226 , H01L27/082 , H03K19/003 , H03K19/091
CPC分类号： H03K19/00353
摘要： PURPOSE:To operate stably a titled circuit with high accuracy, by providing a capacitor between a connecting point of a high-voltage operating circuit I L circuit, and a ground terminal, so that the noise produced from the I L circuit gives no effect on the high-voltage operating circuit. CONSTITUTION:The noise of clock nature appears at an emitter point A of the I L circuit in incorporating the I L circuit to a constant current part of the power supply side. Then, the capacitor C is connected between the point A and the ground terminal to reduce the noise. Thus, a low-frequency current of an analog circuit hardly flows to the capacitor C, but since the clock noise of a high-frequency current flows through the capacitor C into ground, the noise appearing at an output VA of the analog circuit is reduced remarkably.
摘要翻译：目的：通过在高电压工作电路I 2 L电路的连接点与接地端子之间设置电容器，以高精度稳定地标定电路，从而使I <2> L电路对高压工作电路没有影响。构成：将I 2 L电路并入电源侧的恒定电流部分时，时钟性质的噪声出现在I 2 L电路的发射极点A. 然后，电容器C连接在点A和接地端子之间以减小噪声。因此，模拟电路的低频电流几乎不流向电容器C，但是由于高频电流的时钟噪声通过电容器C流入地，所以模拟电路的输出VA处出现的噪声减小显着。

37. 发明专利

JPS5910260A Integrated injection logical circuit 失效
标题翻译：集成注射逻辑电路
公开(公告)号：JPS5910260A
公开(公告)日：1984-01-19
申请号：JP11264483
申请日：1983-06-24
申请人： Hitachi Ltd
发明人： NAKAMURA TOORU , KANEKO KENJI , OKABE TAKAHIRO , NISHIMURA TAKANORI , ANZAI NORIO , TSUNEMATSU MASAYASU , SAKAMOTO ISAO
IPC分类号： H01L27/082 , H01L21/8226 , H01L27/02 , H03K19/091
CPC分类号： H01L27/0233
摘要： PURPOSE:To constitute a plurality of inputs by contacting P type base regions and add multi-input function to an integrated injection logical element without increasing the element area excessively by providing N type poly Si or amorphous Si electrodes. CONSTITUTION:A plurality of poly Si diodes D1-D3 are formed on the base regions which are the input terminals of an integrated injection logical circuit, and cathode sides B1-B3 become the input terminals. An injector region 31 and the base regions 32 and 33 which are P type diffused layers are provided in an N type emitter layer 2 on a P type Si substrate 1, and N type collector regions 41 ane 43 are formed in the base regions 32 and 33. A plurality of electrodes 61 and 62 of the base regin 32 and an electrode 63 which connects a collector region 41 to the base region 33 are all formed of N type poly Si. The diodes D1-D3 are formed at the interfaces between the P type base regions 32 and 33 and the N type electrodes 61, 62 and 63. Wirings can be all formed of poly Si, and accordinly an integrated intjection logical circuit which is highly integrated can be manufactured.
摘要翻译：目的：通过提供N型多晶硅或非晶硅电极，通过接触P型基极区域并将多输入功能添加到集成注入逻辑元件而不增加元件面积而构成多个输入。构成：在作为集成注入逻辑电路的输入端子的基极区域上形成多个多晶硅二极管D1-D3，阴极侧B1-B3成为输入端子。在P型Si衬底1上的N型发射极层2中设置有P型扩散层的注入区域31和基极区域32,33，在基极区域32形成有N个集电体区域41e，基极回收器32的多个电极61和62以及将集电极区域41连接到基极区域33的电极63都由N型多晶硅形成。二极管D1-D3形成在P型基极区域32和33与N型电极61,62和63之间的界面处。布线可以全部由多晶硅形成，并且具有高度集成的集成注入逻辑电路可以制造。

38. 发明专利

JPS5840854A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5840854A
公开(公告)日：1983-03-09
申请号：JP13722882
申请日：1982-08-09
申请人： HITACHI LTD
发明人： WATABE TOMOYUKI , TORIYABE TATSU , OKABE TAKAHIRO , NAKAMURA TOORU , KANEKO KENJI , OKADA YUTAKA
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/082
摘要： PURPOSE:To reduce the area of an emitter equivalently, to decrease currents injected from the base of a reverse NPN element and to increase the speed of an I L by forming an obstacle, such as a shallow N layer, a V-shaped groove, etc. to the base layer of the lateral PNP element of the I L. CONSTITUTION:The shallow N layers 501 are shaped among an injector 41 and the P bases 42 of the reverse NPN elements as the obstacles. The layers 501 are formed at the same time as the N collar 52 of the I L and the N collectors 51 of the reverse NPN are shaped, and may be contacted or stacked to the layers 42, 21. According to this constitution, when the injector is at OV and the base of the reverse NPN element is at VBV, currents injected from the base of the reverse NPN element are decreased, and the lower limit value of the current gains betai of the reverse NPN element required for operating the I L can be lowered. The device can operate at high speed because holes stored among the layers 41, 42 are reduced.

39. 发明专利

JPS5825259A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5825259A
公开(公告)日：1983-02-15
申请号：JP11851082
申请日：1982-07-09
申请人： HITACHI LTD
发明人： KANEKO KENJI , INABA TOORU , OKABE TAKAHIRO , WATABE TOMOYUKI
IPC分类号： H01L27/082 , H01L21/8226 , H01L27/02
摘要： PURPOSE:To reduce the layout area of a circuit by a method wherein a part of a connection wiring between a plurality of I LS is arranged on the base of the pnp transistor of I L through the intermediary of an insulation film. CONSTITUTION:There is a gap between the injector wiring of I L and the base or collector terminal of the pnp transistor thereof. By laying a connection wiring 23 between I Ls through this gap, the number of wirings which have been laid usually on the base of an npn transistor can be reduced, and this method is very effective, in particular, for a cell wherein a collector is wired in parallel to an inductor. By this constitution, an idle space of the npn transistor is reduced, and thereby the layout area of a circuit can be diminished. In addition, it enables the prevention of the useless fall of the current amplification factor of the npn transistor, and the reduction of a junction capacity, and thus the degree of freedom of a design of layout is increased.

40. 发明专利

JPS57197903A OSCILLATING CIRCUIT 失效
公开(公告)号：JPS57197903A
公开(公告)日：1982-12-04
申请号：JP8301782
申请日：1982-05-19
申请人： HITACHI LTD
发明人： KANEKO KENJI , OKABE TAKAHIRO
IPC分类号： H03B5/32 , H03B5/36 , H03K3/02 , H03K3/282 , H03L3/00
摘要： PURPOSE:To shorten the time from a powering-up point to the start of oscillation by connecting two oscillating circuits composed of I L elements in parallel, and using one oscillating circuit as an oscillating circuit and the other as a bias circuit. CONSTITUTION:A circuit D wherein transistors (TR) 1a and 1b, 2a and 2b, and 3a and 3b each constitute one I L circuit, and a circuit E which has the same element size, the same process and the same circuit constitution are formed closely. A quartz oscillator 4 is connected between the points B and C of the circuit D to constitute an oscillating circuit. On the output side of the circuit E used as a bias circuit, a two-collector TR3a' is used; the collector 31 is connected to the base and to constitute a current mirror circuit, and the collector 32 is connected to the point C of the circuit D. The unbalanced current at the point C increases by 1/(1+beta) time as great as that when the circuit D is used independently and becomes much less, where beta is the current amplification factor of the TR3a', so that an oscillation starting time is shortened.

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