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31. 发明授权

US07078764B2 Method of fabricating a vertical quadruple conduction channel insulated gate transistor, and integrated circuit including this kind of transistor 有权
标题翻译：制造垂直四通导通绝缘栅晶体管的方法，以及包括这种晶体管的集成电路
公开(公告)号：US07078764B2
公开(公告)日：2006-07-18
申请号：US10852057
申请日：2004-05-24
申请人： Thomas Skotnicki , Emmanuel Josse
发明人： Thomas Skotnicki , Emmanuel Josse
IPC分类号： H01L29/76
CPC分类号： H01L29/66666 , H01L29/165 , H01L29/7827
摘要： The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1,PL2 extending between the source and drain regions, and forming two very fine pillars.
摘要翻译：垂直绝缘栅晶体管包括在半导体衬底上的垂直柱，其顶部包括源极和漏极区中的一个，位于柱的侧面和衬底顶表面上的栅极电介质层，以及半导体门静置在栅介质层上。源极和漏极区域中的另一个位于柱PIL的底部，并且绝缘栅极包括搁置在柱的侧面上的隔离的外部部分15和位于源极和漏极区域之间的柱内的隔离的内部部分14 。隔离的内部部分通过在源极和漏极区域之间延伸的两个连接半导体区域PL 1，PL 2从隔离的外部部分侧向分离，并形成两个非常细的柱。

32. 发明授权

US07042039B2 Integrated memory circuit for storing a binary datum in a memory cell 有权
标题翻译：用于将二进制数据存储在存储器单元中的集成存储器电路
公开(公告)号：US07042039B2
公开(公告)日：2006-05-09
申请号：US10702066
申请日：2003-11-05
申请人： Pascale Mazoyer , Alexandre Villaret , Thomas Skotnicki
发明人： Pascale Mazoyer , Alexandre Villaret , Thomas Skotnicki
IPC分类号： H01L27/108
CPC分类号： B82Y10/00 , G11C2216/08 , H01L29/788 , H01L29/7881 , H01L29/7888
摘要： An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.
摘要翻译：集成存储器电路包括由单个晶体管形成的至少一个存储单元，其栅极（GR）具有通过包含一系列势阱的绝缘层与沟道区域绝缘的下表面，绝缘层基本上布置在与栅极相距一定距离处并且从基本上平行于栅极的下表面的平面中的沟道区域开始。势阱能够容纳限制在平面中的电荷，并且可以控制其在平面内朝向源极区域旁边的第一限制区域或靠近漏极区域的第二限制区域移动，以便限定两个单元的内存状态。

33. 发明授权

US07038285B2 Very high sensitivity magnetic sensor 有权
标题翻译：非常高灵敏度的磁传感器
公开(公告)号：US07038285B2
公开(公告)日：2006-05-02
申请号：US10149093
申请日：2000-12-06
申请人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
发明人： Hervé Jaouen , Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L29/82
CPC分类号： G10K9/13 , G01D5/242 , G01L9/0042 , Y10T428/1157 , Y10T428/1171 , Y10T428/19
摘要： A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.
摘要翻译：磁传感器包括由导电材料制成的薄的可变形膜，该导电材料形成电容器的第一板，其导通电流。电容器的第二电容器板包括半导体衬底的掺杂区域。气体介质层分离两个板。由于由位于膜的平面中的磁场产生的洛伦兹力的作用并且垂直于通过其传导的电流线，膜变形。此外，还提供了用于制造该磁传感器的工艺以及使用该磁传感器来测量磁场的装置。

34. 发明申请

US20050255682A1 Process for transferring a layer of strained semiconductor material 有权
标题翻译：用于转移应变半导体材料层的工艺
公开(公告)号：US20050255682A1
公开(公告)日：2005-11-17
申请号：US11165339
申请日：2005-06-24
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L21/301 , H01L21/762 , H01L29/10 , C30B1/00 , H01L21/20 , H01L21/36 , H01L21/425
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.
摘要翻译：本发明涉及一种用于制造电子结构的方法，该电子结构包括来自施主晶片的应变半导体材料的薄层。施主晶片具有晶格参数匹配层，其包括具有第一晶格参数的半导体材料的上层和具有与第一晶格参数基本不同的第二标称晶格参数的半导体材料的膜，并且其被应变由匹配层。该方法包括将膜转移到接收衬底。本发明还涉及可以通过该方法生产的半导体结构。

35. 发明授权

US06953736B2 Process for transferring a layer of strained semiconductor material 有权
公开(公告)号：US06953736B2
公开(公告)日：2005-10-11
申请号：US10615259
申请日：2003-07-09
申请人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
发明人： Bruno Ghyselen , Daniel Bensahel , Thomas Skotnicki
IPC分类号： H01L21/301 , H01L21/762 , H01L29/10 , H01L21/30
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259 , Y10S438/938
摘要： The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material having a first lattice parameter and a film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter and that is strained by the matching layer. This process includes transfer of the film to a receiving substrate. The invention also relates to the semiconductor structures that can be produced by the process.

36. 发明授权

US06642108B2 Fabrication processes for semiconductor non-volatile memory device 有权
公开(公告)号：US06642108B2
公开(公告)日：2003-11-04
申请号：US10273925
申请日：2002-10-18
申请人： Thomas Skotnicki , Didier Dutartre , Pascal Ribot , Maryse Paoli , Richard Fournel
发明人： Thomas Skotnicki , Didier Dutartre , Pascal Ribot , Maryse Paoli , Richard Fournel
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , B82Y10/00 , H01L21/28273 , H01L29/42336
摘要： A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

37. 发明授权

US06465332B1 Method of making MOS transistor with high doping gradient under the gate 有权
标题翻译：在栅极下制造具有高掺杂梯度的MOS晶体管的方法
公开(公告)号：US06465332B1
公开(公告)日：2002-10-15
申请号：US09402853
申请日：2000-01-10
申请人： Constantin Papadas , Jorge L. Regolini , Thomas Skotnicki , André Grouillet , Christine Morin
发明人： Constantin Papadas , Jorge L. Regolini , Thomas Skotnicki , André Grouillet , Christine Morin
IPC分类号： H01L2136
CPC分类号： H01L29/66651 , H01L21/2205 , H01L21/26506 , H01L29/7833
摘要： The invention is directed to a method of manufacturing an area of a first type of conductivity extending a depth into a semiconductor substrate and having a doping gradient as a function of the depth into the semiconductor substrate. The method comprises acts of providing a semiconductor substrate of the first type of conductivity; implanting nitrogen in an upper surface of the semiconductor substrate, with a dose in a range of between approximately 5.1013 and 5.1015 at./cm2, annealing the semiconductor substrate; and growing an epitaxial layer on the substrate of the first type of conductivity having a doping level lower than the semiconductor substrate.
摘要翻译：本发明涉及一种制造将深度延伸到半导体衬底中并具有作为半导体衬底的深度的函数的掺杂梯度的第一类型导电区域的方法。该方法包括提供第一类型导电性的半导体衬底的动作; 在半导体衬底的上表面中以约5.1013至5.1015at./cm2的范围内注入氮气，对半导体衬底进行退火; 以及在衬底上生长具有低于半导体衬底的掺杂水平的第一类型导电性的外延层。

38. 发明授权

US08773003B2 Thermoelectric generator 有权
标题翻译：热电发电机
公开(公告)号：US08773003B2
公开(公告)日：2014-07-08
申请号：US13410308
申请日：2012-03-02
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： H02N10/00
CPC分类号： H02N2/18
摘要： A thermoelectric generator including a sheet of a deformable material containing closed cavities, each of which contains a drop of a vaporizable liquid, and a mechanism for transforming into electricity the power resulting from the deformation of the sheet linked to the evaporation/condensation of the liquid.
摘要翻译：一种热电发电机，其包括可变形材料的片材，其包含封闭空腔，每个所述可变形材料包含一滴可蒸发的液体，以及用于将与所述液体的蒸发/冷凝相关联的片材的变形产生的功率转化为电力的机构。

39. 发明授权

US08704386B2 Thermoelectric generator 有权
标题翻译：热电发电机
公开(公告)号：US08704386B2
公开(公告)日：2014-04-22
申请号：US12902355
申请日：2010-10-12
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： F02B63/04 , F01K15/00 , B60L1/02
CPC分类号： F03G7/06 , H02N10/00 , Y02T10/166
摘要： A thermoelectric generator including a membrane maintained by lateral ends and capable of taking a first shape when its temperature reaches a first threshold and a second shape when its temperature reaches a second threshold greater than the first threshold; at least one electrically conductive element attached to with the membrane and connecting the lateral ends of the membrane; and circuitry capable of generating, at the level of the membrane, a magnetic field orthogonal to the membrane displacement direction, the lateral ends of the membrane being connected to output terminals of the generator.
摘要翻译：一种热电发电机，其包括由横向端部保持的膜，当其温度达到第一阈值时，当其温度达到大于第一阈值的第二阈值时能够获得第一形状; 至少一个导电元件与膜连接并连接膜的侧端; 以及能够在膜的水平处产生与膜移位方向正交的磁场的电路，膜的横向端部连接到发生器的输出端子。

40. 发明授权

US08492958B2 Device for converting thermal power into electricity 有权
标题翻译：将火力转换为电力的装置
公开(公告)号：US08492958B2
公开(公告)日：2013-07-23
申请号：US12911267
申请日：2010-10-25
申请人： Thomas Skotnicki
发明人： Thomas Skotnicki
IPC分类号： H02N2/18
CPC分类号： H02N2/18
摘要： A device for converting thermal power into electric power including a plurality of bimetallic strips disposed between a rigid support and a plate of a resilient plastic material; and on the side of the plate of a resilient plastic material opposite to the strips, a layer of a piezoelectric material connected to output terminals, wherein the rigid support is capable of being in contact with a hot source, and the plate of a resilient plastic material is capable of transmitting to the piezoelectric layer the mechanical stress due to the deformations of the bimetallic strips.
摘要翻译：一种用于将热功率转换成电力的装置，包括设置在刚性支撑件和弹性塑料材料板之间的多个双金属条; 并且在与所述条带相反的弹性塑料材料的所述板的一侧上，连接到输出端子的压电材料层，其中所述刚性支撑件能够与热源接触，并且所述弹性塑料板材料能够向压电层传递由于双金属条的变形引起的机械应力。

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