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31. 发明授权

US06780694B2 MOS transistor 有权
标题翻译： MOS晶体管
公开(公告)号：US06780694B2
公开(公告)日：2004-08-24
申请号：US10338930
申请日：2003-01-08
申请人： Bruce B. Doris , Omer H. Dokumaci , Jack A. Mandelman , Carl J. Radens
发明人： Bruce B. Doris , Omer H. Dokumaci , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21338
CPC分类号： H01L21/28114 , H01L21/26586 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/665
摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
摘要翻译：制造半导体晶体管器件的方法包括以下步骤。提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。取出平坦化层。衬底中形成源/漏极扩展，防止短沟道效应。形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。在衬底中形成源/漏区。在T形栅电极的顶部和源极/漏极区之上形成硅化物层。

32. 发明授权

US06632741B1 Self-trimming method on looped patterns 失效
标题翻译：循环模式自修整方法
公开(公告)号：US06632741B1
公开(公告)日：2003-10-14
申请号：US09619664
申请日：2000-07-19
申请人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl J. Radens
发明人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21302
CPC分类号： H01L21/0334
摘要： A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material along the sidewalls of the features in the first material.
摘要翻译：一种自修剪图案的方法包括在沉积在基底上的第一材料中形成包含多个规则或不规则特征的图案，沉积第二材料的共形层，并蚀刻第二材料以形成第二材料的间隔物第一种材料的特征侧壁。

33. 发明授权

US06570207B2 Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex 失效
标题翻译：在使用垂直阵列器件单元复合体的DRAM工艺中创建垂直电容器和反熔丝的结构和方法
公开(公告)号：US06570207B2
公开(公告)日：2003-05-27
申请号：US09736496
申请日：2000-12-13
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L23/5252 , H01L27/10841 , H01L27/10864 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.
摘要翻译：提供一种集成电路芯片，其具有常规DRAM垂直传送装置和可以直接访问的集成垂直存储电容器或反熔丝，而不必打开传输门。直接访问集成电容器或反熔丝的机构可以是垂直单元内的修改的掺杂分布，其提供低电阻穿通FET。或者，机构可以是垂直单元内的一对重叠或几乎重叠的扩散。

34. 发明授权

US06538295B1 Salicide device with borderless contact 有权
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06538295B1
公开(公告)日：2003-03-25
申请号：US09645499
申请日：2000-08-25
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

35. 发明授权

US06518119B2 Strap with intrinsically conductive barrier 失效
标题翻译：带本征导电屏障
公开(公告)号：US06518119B2
公开(公告)日：2003-02-11
申请号：US09886065
申请日：2001-06-21
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L29/945
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

36. 发明授权

US06455886B1 Structure and process for compact cell area in a stacked capacitor cell array 失效
标题翻译：叠层电容器阵列中紧凑单元面积的结构和工艺
公开(公告)号：US06455886B1
公开(公告)日：2002-09-24
申请号：US09636564
申请日：2000-08-10
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L29/66181
摘要： A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a trough in a substrate above a buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at a contact area of an active region between adjacent word lines. The active region is rhomboid in shape, enabling a low capacitor contact resistance, a small bit line and word line pitch, and consequently, a compact capacitor cell.
摘要翻译：一种用于形成的方法，以及具有连接到层叠电容器单元的垂直取向的晶体管的半导体器件的结构，其中电容器的接触面积使得能够实现紧凑的电池。垂直取向的晶体管形成在掩埋位线上方的衬底的槽中。栅极导体可以形成在掩埋位线上方的槽中，源极和漏极扩散沿着槽的侧壁间隔开。在半导体衬底中形成隔离区以隔离晶体管。在与掩埋位线的方向垂直的方向上在半导体衬底的表面上形成字线。在相邻字线之间的有源区域的接触区域处，在半导体衬底的表面上方形成电容器触点。有源区域是菱形形状，能够实现低电容器接触电阻，小位线和字线间距，从而实现紧凑的电容器单元。

37. 发明授权

US06440872B1 Method for hybrid DRAM cell utilizing confined strap isolation 失效
标题翻译：混合DRAM单元利用限制带隔离的方法
公开(公告)号：US06440872B1
公开(公告)日：2002-08-27
申请号：US09706468
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
IPC分类号： H01L2100
CPC分类号： H01L27/10867 , H01L27/10876
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.
摘要翻译：形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

38. 发明授权

US06414347B1 Vertical MOSFET 失效
标题翻译：垂直MOSFET
公开(公告)号：US06414347B1
公开(公告)日：2002-07-02
申请号：US09790011
申请日：2001-02-09
申请人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
发明人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
IPC分类号： H01L2972
CPC分类号： H01L27/10864 , H01L21/2255 , H01L21/26586 , H01L27/10841 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
摘要翻译：一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。

39. 发明授权

US06380027B2 Dual tox trench dram structures and process using V-groove 失效
标题翻译：双毒tox沟结构和工艺采用V型槽
公开(公告)号：US06380027B2
公开(公告)日：2002-04-30
申请号：US09225127
申请日：1999-01-04
申请人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
发明人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
IPC分类号： H01L21242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10894
摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
摘要翻译：用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及其中所述第一氧化物比所述第二氧化物厚。

40. 发明授权

US06261894B1 Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays 有权
标题翻译：在EDRAM阵列中形成双功能高性能支持MOSFET的方法
公开(公告)号：US06261894B1
公开(公告)日：2001-07-17
申请号：US09706492
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L218234
CPC分类号： H01L27/10864 , H01L27/10894 , H01L27/10897
摘要： Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in the forming memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/ EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.
摘要翻译：提供双功能功能高性能支持金属氧化物半导体场效应晶体管（MOSFET）/嵌入式动态随机存取（EDRAM）阵列的方法。这里描述的方法减少了在形成存储器结构中使用的深UV掩模的数量，解耦支持和排列处理步骤，提供盐化栅极，源极/漏极区域和位线，并且在一些情况下提供局部互连，加工成本。还提供了双功能功能的高性能支持具有栅极导体保护环和/或局部互连的MOSFET / EDRAM阵列。

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