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31. 发明授权

US5986304A Punch-through prevention in trenched DMOS with poly-silicon layer covering trench corners 失效
标题翻译：在沟槽DMOS中进行穿透防止，多晶硅层覆盖沟槽角
公开(公告)号：US5986304A
公开(公告)日：1999-11-16
申请号：US782368
申请日：1997-01-13
申请人： Fwu-Iuan Hshieh , Koon Chong So , True-Lon Lin
发明人： Fwu-Iuan Hshieh , Koon Chong So , True-Lon Lin
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/4238
摘要： The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region. The conductive material filling the trenches including punch-through suppressing blocks covering corners of the cell defined by the intersecting trenches wherein the source region disposed underneath the corners immediately next to the trenches having a lower net concentration of impurities of the first conductivity type than remaining portion of the source region.
摘要翻译：本发明包括具有第一导电类型的衬底，其顶表面包括设置在其中的至少两个相交的沟槽，其中衬有沟槽的绝缘层和填充沟槽的导电材料。晶体管还包括第一导电类型的源极区域，从邻近沟槽的衬底的顶表面朝向衬底延伸。晶体管还具有与第一导电类型相反极性的第二导电类型的主体区域，主体区域从与沟槽相邻的顶表面延伸到衬底并围绕源极区域。填充沟槽的导电材料包括覆盖由相交沟槽限定的电池角部的穿通抑制块，其中设置在紧邻沟槽的角下方的源极区域具有比剩余部分更低的第一导电类型的杂质的净浓度的源地区。

32. 发明授权

US5907169A Self-aligned and process-adjusted high density power transistor with gate sidewalls provided with punch through prevention and reduced JFET resistance 失效
标题翻译：自对准和工艺调节的高密度功率晶体管，栅极侧壁提供穿孔防止和减小的JFET电阻
公开(公告)号：US5907169A
公开(公告)日：1999-05-25
申请号：US844165
申请日：1997-04-18
申请人： Fwu-Iuan Hshieh , True-Lon Lin , Koon Chong So
发明人： Fwu-Iuan Hshieh , True-Lon Lin , Koon Chong So
IPC分类号： H01L21/28 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L21/28114 , H01L21/2815 , H01L29/402 , H01L29/0638 , H01L29/0847 , H01L29/4232 , H01L29/4238
摘要： The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary. The MOSFET transistor further includes a thin gate oxide layer overlying the top surface of the substrate and an edge of the raised oxide terrace. The MOSFET transistor further includes a polysilicon gate overlaying the oxide block and the silicon terrace, the gate further covering an area above the source region and the body region insulated by the gate oxide layer therefrom.
摘要翻译：本发明公开了一种支撑在基板上的MOSFET晶体管。 MOSFET晶体管包括在衬底的顶表面附近限定其中的漏极区的第一导电类型的外延层。 MOSFET晶体管还包括负载在外延层的凸起的硅平台上的氧化物块，该外延层设置在晶体管的中心部分的第一导电类型比外延层高的掺杂剂浓度的JFET还原区之上。 MOSFET晶体管还包括围绕设置在顶表面附近并限定MOSFET晶体管的边界的JFET还原区的第二导电类型的下外体体区域。 MOSFET晶体管还包括封装在设置在顶表面附近并延伸到晶体管边界的下外体体区中的第一导电类型的源极区域。 MOSFET晶体管还包括覆盖在衬底的顶表面上的薄栅极氧化物层和凸起的氧化物露台的边缘。所述MOSFET晶体管还包括覆盖所述氧化物块和所述硅平台的多晶硅栅极，所述栅极还覆盖所述源极区域上方的区域以及由所述栅极氧化物层绝缘的所述主体区域。

33. 发明授权

US5729037A MOSFET structure and fabrication process for decreasing threshold voltage 失效
标题翻译： MOSFET结构和降低阈值电压的制造工艺
公开(公告)号：US5729037A
公开(公告)日：1998-03-17
申请号：US638639
申请日：1996-04-26
申请人： Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Danny Chi Nim , Koon Chong So
发明人： Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Danny Chi Nim , Koon Chong So
IPC分类号： H01L21/336 , H01L29/36 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66712 , H01L29/086 , H01L29/1095 , H01L29/7811 , H01L29/36
摘要： Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve a low threshold voltage. The improved MOSFET device is formed in a semiconductor substrate with a drain region formed near a bottom surface of the substrate supporting a plurality of double-diffused vertical cells thereon wherein each of the vertical cells including a pn-junction having a body region surrounding a source region and each of the vertical cell further including a gate above the pn-junction. Each of the vertical cells further includes a source-dopant segregation reduction layer for reducing a surface segregation between the source region and an oxide layer underneath the gate whereby the body surface peak dopant concentration near an interface between the source region and the body region is reduced for reducing a threshold voltage of the MOSFET device. In another preferred embodiment, the source-dopant segregation reduction layer includes a LPCVD nitride layer formed on top of the polysilicon gates.
摘要翻译：在本发明中公开了改进的功率MOSFET结构和制造工艺以实现低阈值电压。改进的MOSFET器件形成在半导体衬底中，其中在衬底的底表面附近形成有漏极区域，该漏极区域支撑多个双扩散垂直电池，其中每个垂直单元包括具有围绕源极的体区的pn结区域，并且每个垂直单元还包括在pn结上方的栅极。每个垂直单元还包括用于减少源极区域和栅极之下的氧化物层之间的表面偏析的源极 - 掺杂剂偏析还原层，从而源极区域和体区域之间的界面附近的体表面峰值掺杂剂浓度降低用于降低MOSFET器件的阈值电压。在另一个优选的实施方案中，源 - 掺杂剂分离还原层包括形成在多晶硅栅极顶部的LPCVD氮化物层。

34. 发明授权

US07049194B2 Trench DMOS device with improved drain contact 有权
公开(公告)号：US07049194B2
公开(公告)日：2006-05-23
申请号：US10725326
申请日：2003-12-01
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

35. 发明授权

US06849899B2 High speed trench DMOS 有权
标题翻译：高速沟DMOS
公开(公告)号：US06849899B2
公开(公告)日：2005-02-01
申请号：US10673887
申请日：2003-09-29
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/336 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/4925 , H01L29/4933
摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
摘要翻译：提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

36. 发明授权

US06621107B2 Trench DMOS transistor with embedded trench schottky rectifier 失效
标题翻译：沟槽DMOS晶体管采用嵌入式沟道肖特基整流器
公开(公告)号：US06621107B2
公开(公告)日：2003-09-16
申请号：US09938253
申请日：2001-08-23
申请人： Richard A. Blanchard , Fwu-Iuan Hshieh , Koon Chong So
发明人： Richard A. Blanchard , Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2974
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/7806 , H01L29/872
摘要： A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.
摘要翻译：合并器件包括多个MOSFET单元和多个肖特基整流器单元，以及其设计和制造方法。根据本发明的实施例，MOSFET单元包括：（a）形成在半导体区域的上部内的第一导电类型的源极区域，（b）形成在半导体区域的中间部分内的第二导电类型的体区域半导体区域，（c）形成在半导体区域的下部内的第一导电类型的漏极区域，以及（d）设置在源极区域，体区域和漏极区域附近的栅极区域。该实施例中的肖特基二极管电池设置在沟槽网络内，并且包括与半导体区域的下部肖特基整流接触的导体部分。在该实施例中，至少一个MOSFET单元栅极区沿着沟槽网络的侧壁定位并且邻近至少一个肖特基二极管单元。

37. 发明授权

US06558984B2 Trench schottky barrier rectifier and method of making the same 有权
标题翻译：沟槽肖特基势垒整流器及其制作方法
公开(公告)号：US06558984B2
公开(公告)日：2003-05-06
申请号：US10078994
申请日：2002-02-19
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L21332
CPC分类号： H01L29/66143 , H01L29/417 , H01L29/872
摘要： A trench Schottky barrier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of a first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on the bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.
摘要翻译：沟槽肖特基势垒及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。整流器还包括覆盖沟槽底部的半导体区域和沟槽侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域的多晶硅区域和氧化物层的一部分。

38. 发明授权

US06475884B2 Devices and methods for addressing optical edge effects in connection with etched trenches 有权
标题翻译：用于寻址与蚀刻沟槽有关的光学边缘效应的设备和方法
公开(公告)号：US06475884B2
公开(公告)日：2002-11-05
申请号：US09924855
申请日：2001-08-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2136
CPC分类号： H01L29/7813 , H01L21/3083 , H01L29/7811
摘要： In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (1) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity type in the body region adjacent to the each internal trench, but not adjacent to the at least one peripheral trench.
摘要翻译：在本发明的第一方面中，提供了一种改进的半导体衬底。改性基板包括：（1）半导体衬底; （2）在衬底的至少一部分上提供的至少一个缓冲层; 和（3）多个沟槽，包括（a）延伸到半导体衬底中的多个内部沟槽和（b）延伸到至少一个缓冲层中但不延伸到半导体衬底中的至少一个浅外围沟槽。另一方面，提供了一种在半导体衬底中选择性地提供沟槽的方法。根据本发明的另一方面，提供了包括至少一个外围沟槽和多个内部沟槽的沟槽DMOS晶体管结构。该结构包括：（1）第一导电类型的衬底; （2）具有第二导电类型的衬底上的主体区域，其中所述外围和内部沟槽延伸穿过所述身体区域; （3）对每个外围和内部沟槽进行排列的绝缘层; （4）覆盖每个绝缘层的第一导电电极; 和（5）与所述每个内部沟槽相邻但不与所述至少一个周边沟槽相邻的所述主体区域中的所述第一导电类型的源极区域。

39. 发明授权

US06420768B1 Trench schottky barrier rectifier and method of making the same 有权
标题翻译：沟槽肖特基势垒整流器及其制作方法
公开(公告)号：US06420768B1
公开(公告)日：2002-07-16
申请号：US09737357
申请日：2000-12-15
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L27095
CPC分类号： H01L29/66143 , H01L29/417 , H01L29/872
摘要： A trench Schottky barrier rectifier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.
摘要翻译：沟槽肖特基势垒整流器及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。整流器还包括覆盖沟槽底部的半导体区域和沟槽的侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域多晶硅区域和氧化物层的一部分。

40. 发明授权

US06376315B1 Method of forming a trench DMOS having reduced threshold voltage 有权
标题翻译：形成具有降低的阈值电压的沟槽DMOS的方法
公开(公告)号：US06376315B1
公开(公告)日：2002-04-23
申请号：US09540856
申请日：2000-03-31
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/1095
摘要： A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.
摘要翻译：提供制造一个或多个沟槽DMOS晶体管的方法。在该方法中，提供与一个或多个沟槽相邻的一个或多个或多个主体区域。一个或多个沟槽衬有第一绝缘层。第一绝缘层的一部分至少沿着沟槽的上侧壁去除，暴露身体区域的部分。然后在身体区域的至少暴露部分上形成氧化物层，导致与氧化物层相邻的体区内的载流子浓度降低的区域。体内区域中多数载流子浓度的这种修改是有利的，因为可以在DMOS晶体管内建立低阈值电压，而不需要使用更薄的栅极氧化物（这将降低产率和开关速度），而且基本上不增加冲击的可能性 -通过。

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