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31. 发明申请

WO2013078867A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013078867A1
公开(公告)日：2013-06-06
申请号：PCT/CN2012/078571
申请日：2012-07-12
申请人： LI, Yuan , GUO, Lei
发明人： LI, Yuan , GUO, Lei
IPC分类号： H01L33/16 , H01L33/02 , H01L33/00
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/0242 , H01L21/0243 , H01L21/02433 , H01L21/02609 , H01L21/02658 , H01L21/0275 , H01L29/04 , H01L29/0692 , H01L33/007 , H01L33/16 , H01L33/20 , H01L33/24 , H01L33/32
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (100); and a plurality of convex structures (200) formed on a surface of the substrate (100) and arranged in a longitudinal direction of the substrate (100), each convex structure (200) having a top surface (202), a bottom surface (204) located on the surface of the substrate, a first end surface (206) and a second end surface (208) parallel to each other, and a front side surface (210) and a rear side surface (212) parallel to each other, in which the rear side surface (212) of one of two adjacent convex structures (200) and the front side surface (210) of the other are located on a same plane to allow the plurality of convex structures (200) to form a zigzag structure.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：衬底（100）; 以及形成在所述基板（100）的表面上且沿着所述基板（100）的长度方向配置的多个凸部结构（200），每个凸起结构（200）具有顶面（202），底面 204），位于所述基板的表面上的第一端面（206）和彼此平行的第二端面（208）以及彼此平行的前侧表面（210）和后侧表面（212），其中两个相邻凸起结构（200）中的一个的后侧表面（212）和另一个的前侧表面（210）位于同一平面上，以允许所述多个凸起结构（200）形成曲折结构。

32. 发明申请

WO2012100519A1 GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：导通绝缘体结构及其形成方法
公开(公告)号：WO2012100519A1
公开(公告)日：2012-08-02
申请号：PCT/CN2011/077703
申请日：2011-07-27
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L29/78684 , H01L21/76256 , H01L29/4908 , H01L29/7842 , H01L29/78603 , H01L29/78609
摘要： A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.
摘要翻译：提供一种形成绝缘体上Ge结构的方法，包括以下步骤：在衬底（2000）上形成Ge层（1200）; 处理所述Ge层（1200）的第一表面以形成第一半导体金属 - 锗化物钝化层（1300）; 将第一半导体金属 - 锗化物钝化层（1300）与硅衬底（1100）接合，其中在所述硅衬底（1100）的表面上形成氧化物绝缘层; 并移除基板（2000）。此外，还提供了通过该方法形成的绝缘体上Ge结构。

33. 发明申请

WO2011147256A1 LOW SCHOTTKY BARRIER SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：低肖特基二极管半导体结构及其形成方法
公开(公告)号：WO2011147256A1
公开(公告)日：2011-12-01
申请号：PCT/CN2011/073904
申请日：2011-05-10
申请人： TSINGHUA UNIVERSITY , WANG, Jing , WANG, Wei , GUO, Lei , XU, Jun
发明人： WANG, Jing , WANG, Wei , GUO, Lei , XU, Jun
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/0895 , H01L29/1054 , H01L29/41783 , H01L29/517 , H01L29/66477 , H01L29/66643 , H01L29/78 , H01L29/7839
摘要： A low Schottky barrier semiconductor structure is provided. The structure comprises: a substrate (100); a SiGe layer with low Ge content formed on the substrate; a channel layer (900) with high Ge content formed on the SiGe layer; a gate stack (200) formed on the substrate and a sidewall (400) of one or more layers formed on both sides of the gate stack; metal source/drain (300) formed in the channel layer and on the both sides of the gate stack, respectively; and an insulation layer (600) formed between the substrate and the metal source and between the substrate and the metal drain, respectively. A method for forming the low Schottky barrier semiconductor structure is also provided.
摘要翻译：提供了一种低肖特基势垒半导体结构。该结构包括：基底（100）; 在基板上形成具有低Ge含量的SiGe层; 在SiGe层上形成具有高Ge含量的沟道层（900）; 形成在所述基板上的栅极堆叠（200）和形成在所述栅极堆叠的两侧上的一个或多个层的侧壁（400）金属源极/漏极（300）分别形成在沟道层和栅极堆叠的两侧; 以及形成在所述基板和所述金属源之间以及所述基板和所述金属排出口之间的绝缘层（600）。还提供了形成低肖特基势垒半导体结构的方法。

34. 发明申请

WO2013152707A1 CLOCK SIGNAL TRANSMISSION APPARATUS 审中-公开
标题翻译：时钟信号传输装置
公开(公告)号：WO2013152707A1
公开(公告)日：2013-10-17
申请号：PCT/CN2013/073921
申请日：2013-04-09
申请人： GUO, Lei , LI, Yuan
发明人： GUO, Lei , LI, Yuan
IPC分类号： H01L27/15
CPC分类号： G09G3/32 , G06F1/105 , H01L25/0753 , H01L33/60 , H01L2924/0002 , H04B10/803 , H01L2924/00
摘要： A clock signal transmission apparatus is provided. The clock signal transmission apparatus comprises: a modulator (4) for receiving a clock signal and modulating a light emitting device (2) according to the clock signal; the light emitting device (2) for emitting a light signal corresponding to the clock signal; and an integrated circuit chip (1) comprising: at least one light-to-electricity converter (11) for converting the light signal into an electric signal, and at least one demodulator (13) for demodulating the electric signal to obtain the clock signal.
摘要翻译：提供时钟信号发送装置。时钟信号传输装置包括：调制器（4），用于接收时钟信号并根据时钟信号调制发光器件（2）; 所述发光装置（2）用于发射对应于所述时钟信号的光信号; 以及集成电路芯片（1），包括：用于将所述光信号转换为电信号的至少一个光电转换器（11），以及用于解调所述电信号以获得所述时钟信号的至少一个解调器（13）。

35. 发明申请

WO2013120223A1 SMART 3GDT 审中-公开
公开(公告)号：WO2013120223A1
公开(公告)日：2013-08-22
申请号：PCT/CN2012/000175
申请日：2012-02-14
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , LIU, Di , XIA, Qi , DING, Huiping , SHA, Ping , QU, Zhiwei , YU, Zhao , GUO, Lei
发明人： LIU, Di , XIA, Qi , DING, Huiping , SHA, Ping , QU, Zhiwei , YU, Zhao , GUO, Lei
IPC分类号： H04W48/00
CPC分类号： H04W76/23 , H04L43/0894 , H04W24/04 , H04W24/08 , H04W76/22
摘要： A smart 3GDT schema has been disclosed, in detail, a method for controlling the communication of a network system has bee disclosed. The network system comprises a UE, a NodeB, a RNC, a SGSN, and a GW. The UE is arranged to be in communication with the RNC via the NodeB, and the RNC is arranged to be in communication with the SGSN which in turn being arranged to be in communication with the GW for non-3 GDT communication of the network system, or the RNC is arranged to be in communication with the GW for 3 GDT communication of the network system. In this method, statistics of payload transferred between the UE and the GW has been monitored, and if the statistics of payload within a predetermined time period exceeds a fist threshold, and the UE is in the non-3 GDT communication, then switching the non-3 GDT communication to the 3 GDT communication. The present application has also disclosed the SGSN, GW, and the network system adaptive to perform the method.
摘要翻译：已经公开了一种智能3GDT模式，其中公开了一种用于控制网络系统通信的方法。网络系统包括UE，NodeB，RNC，SGSN和GW。 UE经由NodeB与RNC通信，RNC被安排为与SGSN通信，SGSN又与GW进行通信，用于网络系统的非3 GDT通信，或者RNC被布置成与GW通信，用于网络系统的3GTT通信。在该方法中，已经监视了UE和GW之间传输的有效载荷的统计信息，并且如果在预定时间段内的有效载荷的统计信息超过了第一阈值，并且UE处于非3 GDT通信中， -3 GDT通信到3 GDT通信。本申请还公开了SGSN，GW和自适应网络系统来执行该方法。

36. 发明申请

WO2013117155A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013117155A1
公开(公告)日：2013-08-15
申请号：PCT/CN2013/071398
申请日：2013-02-05
申请人： GUO, Lei , LI, Yuan
发明人： GUO, Lei , LI, Yuan
IPC分类号： H01L21/20 , H01L33/00 , H01L29/02 , H01L21/02
CPC分类号： H01L29/1075 , H01L21/0237 , H01L21/02439 , H01L21/02521 , H01L21/02639 , H01L21/02647 , H01L29/2003
摘要： A method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate (100); forming a first single crystal semiconductor layer (200) on the substrate (100); etching the first single crystal semiconductor layer (200) to form a plurality of holes or trenches extending to a top surface of the substrate (100), or etching the first single crystal semiconductor layer (200) and the substrate (100) to form a plurality of holes or trenches extending into the substrate (100); etching the substrate (100) through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate (100), thus forming a patterned structure on the porous structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer (300) on the patterned structure.
摘要翻译：提供一种形成半导体结构的方法。该方法包括以下步骤：提供衬底（100）; 在所述基板（100）上形成第一单晶半导体层（200）; 蚀刻第一单晶半导体层（200）以形成延伸到衬底（100）的顶表面的多个孔或沟槽，或蚀刻第一单晶半导体层（200）和衬底（100）以形成多个孔或沟槽延伸到衬底（100）中; 通过所述多个孔或沟槽蚀刻所述衬底（100）以在所述衬底（100）的顶表面下方的区域中形成多孔结构，从而在所述多孔结构上形成图案化结构; 以及沉积单晶半导体材料以在所述图案化结构上形成第二单晶半导体层（300）。

37. 发明申请

WO2013117153A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013117153A1
公开(公告)日：2013-08-15
申请号：PCT/CN2013/071388
申请日：2013-02-05
申请人： GUO, Lei , LI, Yuan
发明人： GUO, Lei , LI, Yuan
IPC分类号： H01L21/02
CPC分类号： H01L29/1075 , H01L21/0237 , H01L21/02439 , H01L21/02521 , H01L21/02639 , H01L21/02647 , H01L21/0265 , H01L29/2003
摘要： A method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate (100); forming a first single crystal semiconductor layer (200) on the substrate (100); etching the first single crystal semiconductor layer (200) to form a plurality of holes or trenches extending to a top surface of the substrate (100), or etching the first single crystal semiconductor layer (200) and the substrate (100) to form a plurality of holes or trenches extending into the substrate (100); etching the substrate (100) through the plurality of holes or trenches to form a plurality of supporting structures (1001) in a region under the top surface of the substrate (100), thus forming a patterned structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer (300) on the patterned structure.
摘要翻译：提供一种形成半导体结构的方法。该方法包括以下步骤：提供衬底（100）; 在所述基板（100）上形成第一单晶半导体层（200）; 蚀刻第一单晶半导体层（200）以形成延伸到衬底（100）的顶表面的多个孔或沟槽，或蚀刻第一单晶半导体层（200）和衬底（100），以形成多个孔或沟槽延伸到衬底（100）中; 通过所述多个孔或沟槽蚀刻所述衬底（100）以在所述衬底（100）的顶表面下方的区域中形成多个支撑结构（1001），从而形成图案化结构; 以及沉积单晶半导体材料以在所述图案化结构上形成第二单晶半导体层（300）。

38. 发明申请

WO2013067969A1 SEMICONDUCTOR VOLTAGE TRANSFORMATION STRUCTURE 审中-公开
标题翻译：半导体电压转换结构
公开(公告)号：WO2013067969A1
公开(公告)日：2013-05-16
申请号：PCT/CN2012/084417
申请日：2012-11-09
申请人： GUO, Lei
发明人： GUO, Lei
IPC分类号： H01L31/12
CPC分类号： H01L31/125 , H01L31/173
摘要： A semiconductor voltage transformation structure is provided. The semiconductor voltage transformation structure comprises: a first electrode layer (100); an electricity-to-light conversion layer (102) formed on the first electrode layer (100); a second electrode layer (104) formed on the electricity-to-light conversion layer (102); a first isolation layer (106) formed on the second electrode layer (104); a third electrode layer formed (108) on the first isolation layer (106); a light-to-electricity conversion layer (110) formed on the third electrode layer (108); and a fourth electrode layer ( 112 ) formed on the light-to-electricity conversion layer (110), in which the first isolation layer (106), the second electrode layer (104) and the third electrode layer (108) are transparent to a working light emitted by the electricity-to-light conversion layer (102).
摘要翻译：提供了半导体电压转换结构。半导体电压转换结构包括：第一电极层（100）; 形成在所述第一电极层（100）上的电光转换层（102）。形成在所述电光转换层（102）上的第二电极层（104）。形成在第二电极层（104）上的第一隔离层（106）; 在第一隔离层（106）上形成的第三电极层（108）; 形成在所述第三电极层（108）上的光电转换层（110）。以及形成在所述光电转换层（110）上的第四电极层（112），其中所述第一隔离层（106），所述第二电极层（104）和所述第三电极层（108）对于由电 - 光转换层（102）发射的工作光。

39. 发明申请

WO2012163049A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2012163049A1
公开(公告)日：2012-12-06
申请号：PCT/CN2011/082112
申请日：2011-11-11
申请人： TSINGHUA UNIVERSITY , WANG, Jing , GUO, Lei
发明人： WANG, Jing , GUO, Lei
IPC分类号： H01L29/06 , H01L29/24 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/778 , H01L21/764 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/66431
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a Si substrate (1100); a plurality of convex structures (1200) formed on the Si substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures (1200) is less than 50nm in width; a first semiconductor film (1300), in which the first semiconductor film (1300) is formed between the every two adjacent convex structures (1200) and connected with tops of the every two adjacent convex structures (1200); a buffer layer (2100) formed on the first semiconductor film (1300); and a high-mobility III-V compound semiconductor layer (2000) formed on the buffer layer (2100).
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：Si衬底（1100）; 形成在Si衬底（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案被空腔隔开，并且每两个相邻凸起结构（1200）之间的空腔是宽度小于50nm; 第一半导体膜（1300），其中第一半导体膜（1300）形成在每两个相邻的凸起结构（1200）之间并与每两个相邻凸起结构（1200）的顶部连接; 形成在所述第一半导体膜（1300）上的缓冲层（2100）; 和形成在缓冲层（2100）上的高迁移率III-V族化合物半导体层（2000）。

40. 发明申请

WO2012159348A1 DEVICE AND METHOD FOR FIELD EXPANSION 审中-公开
标题翻译：用于现场扩展的装置和方法
公开(公告)号：WO2012159348A1
公开(公告)日：2012-11-29
申请号：PCT/CN2011/077689
申请日：2011-07-27
申请人： 3M INNOVATIVE PROPERTIES COMPANY , ZHANG, Ming , YANG, Jinquan , HUANG, Zheng , XU, Zhigang , MA, Jiangjiang , GUO, Lei
发明人： ZHANG, Ming , YANG, Jinquan , HUANG, Zheng , XU, Zhigang , MA, Jiangjiang , GUO, Lei
IPC分类号： B29C61/00 , H02G15/18
CPC分类号： H02G15/1826 , B29C55/24 , B29C61/065 , B29C63/18 , B29K2021/00 , H02G15/182 , Y10T29/4987 , Y10T29/53391 , Y10T29/53657
摘要： A device and a method for a field expansion. A support core (30) is inserted into the device by a field expansion apparatus. The field expansion apparatus has a pressure applying means (20) defining a radially expandable inner surface and a flat surface radially outwardly extending from the radially expandable inner surface. The device comprises an elastomeric tubing (10) and an adapter (40). The elastomeric tubing (10) has a forward end opposite a rearward end and an axial bore extending therethrough configured to receive the support core (30). The adapter (40) has a step portion (41) defined by a radial outer surface (42) and a flat surface (43) radially outwardly extending from the radial outer surface (42), and an axial bore (44) extending therethrough. The axial bore (44) has a diameter substantially the same as the diameter of the axial bore (12) of the elastomeric tubing (10). The adapter (40) is positioned substantially coaxially with the elastomeric tubing (10) between the pressure applying means (20) and the elastomeric tubing (10) such that, in response to inserting the support core (30) from the rearward end into the elastomeric tubing (10), the flat surface of the adapter (40) is pushed against the flat surface of the pressure applying means (20) by the elastomeric tubing (10); the interface between a rearward end of the adapter (40) and the forward end of the elastomeric tubing (10) is of high friction so that the adapter (40) and the elastomeric tubing (10) expand radially in unison, and the radial outer surface of the adapter (40) exerts a radially outward pressure against the radially expandable inner surface of the pressure applying means (20). device and method for field expansiondevice and method for field expansion
摘要翻译：一种用于现场扩展的设备和方法。通过现场扩张装置将支撑芯（30）插入到装置中。场扩展装置具有限定径向可膨胀的内表面的压力施加装置（20）和从径向可膨胀的内表面径向向外延伸的平坦表面。该装置包括弹性管（10）和适配器（40）。弹性体管道（10）具有与后端相对的前端和延伸穿过其构造成接纳支撑芯（30）的轴向孔。适配器（40）具有由径向外表面（42）和从径向外表面（42）径向向外延伸的平坦表面（43）和从其延伸的轴向孔（44）限定的台阶部分（41）。轴向孔（44）具有与弹性管（10）的轴向孔（12）的直径基本相同的直径。适配器（40）与压力施加装置（20）和弹性体管（10）之间的弹性体管（10）基本上同轴地定位，使得响应于从后端将支撑芯（30）插入到弹性管（10），适配器（40）的平坦表面通过弹性管（10）推压到压力施加装置（20）的平坦表面上。适配器（40）的后端与弹性体管道（10）的前端之间的界面具有高摩擦力，使得适配器（40）和弹性体管道（10）一致地径向扩张，并且径向外部适配器（40）的表面对压力施加装置（20）的径向可膨胀的内表面施加径向向外的压力。现场扩展设备和方法，现场扩展方法

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