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31. 发明申请

US20060160361A1 Nickel salicide process and method of fabricating a semiconductor device using the same 审中-公开
标题翻译：镍硅化硅工艺及使用其制造半导体器件的方法
公开(公告)号：US20060160361A1
公开(公告)日：2006-07-20
申请号：US11303746
申请日：2005-12-15
申请人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung
发明人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Hyun-Su Kim , Eun-Ji Jung
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/324 , H01L29/4933 , H01L29/6659 , H01L29/7833
摘要： A method of forming a silicide layer includes forming a metal layer on a substrate having a silicon region, the metal layer including nickel, annealing the substrate and the metal layer to form the silicide layer on the silicon region, the silicide layer including nickel, and cooling the substrate and the silicide layer at a temperature of about 100° C. to about 300° C. for at least one minute, the cooling occurring after the annealing.
摘要翻译：形成硅化物层的方法包括在具有硅区域的基底上形成金属层，该金属层包括镍，退火基板和金属层，以在硅区域上形成硅化物层，所述硅化物层包括镍，以及在约100℃至约300℃的温度下将衬底和硅化物层冷却至少一分钟，冷却在退火之后发生。

32. 发明申请

US20060091436A1 Methods of forming field effect transistors having metal silicide gate electrodes 有权
标题翻译：形成具有金属硅化物栅电极的场效应晶体管的方法
公开(公告)号：US20060091436A1
公开(公告)日：2006-05-04
申请号：US11230586
申请日：2005-09-20
申请人： Hyun-Su Kim , Jong-Ho Yun , Byung-Hak Lee , Eun-Ji Jung , Gil-Heyun Choi
发明人： Hyun-Su Kim , Jong-Ho Yun , Byung-Hak Lee , Eun-Ji Jung , Gil-Heyun Choi
IPC分类号： H01L29/94
CPC分类号： H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/665 , H01L29/66545
摘要： Methods of forming field effect transistors according to embodiments of the invention include forming a conductive gate electrode (e.g., polysilicon gate electrode) on a semiconductor substrate and forming a first metal layer on the conductive gate electrode. This first metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The first metal layer and the conductive gate electrode are thermally treated for a sufficient duration to convert a first portion of the conductive gate electrode into a first metal silicide region. The first metal layer and the first metal silicide region are then removed to expose a second portion of the conductive gate electrode. A second metal layer is then formed on the second portion of the conductive gate electrode. This second metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The second metal layer and the second portion of the conductive gate electrode are thermally treated for a sufficient duration to thereby convert the second portion of the conductive gate electrode into a second metal silicide region.
摘要翻译：根据本发明的实施例的形成场效应晶体管的方法包括在半导体衬底上形成导电栅电极（例如，多晶硅栅电极），并在导电栅电极上形成第一金属层。该第一金属层可以包括选自镍，钴，钛，钽和钨的材料。对第一金属层和导电栅电极进行热处理足够的时间以将导电栅电极的第一部分转换成第一金属硅化物区域。然后去除第一金属层和第一金属硅化物区域以暴露导电栅电极的第二部分。然后在导电栅电极的第二部分上形成第二金属层。该第二金属层可以包括选自镍，钴，钛，钽和钨的材料。第二金属层和导电栅电极的第二部分被热处理足够的持续时间，从而将导电栅电极的第二部分转换成第二金属硅化物区域。

33. 发明申请

US20060063380A1 Salicide process and method of fabricating semiconductor device using the same 有权
标题翻译：硅化物工艺及其制造使用其的半导体器件的方法
公开(公告)号：US20060063380A1
公开(公告)日：2006-03-23
申请号：US11199439
申请日：2005-08-08
申请人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
发明人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.
摘要翻译：形成金属硅化物层的方法包括将金属层转化为金属硅化物层的基于对流的退火步骤。这些方法可以包括在衬底上形成硅层并形成与硅层直接接触的金属层（例如，镍层）。然后执行步骤以将至少一部分金属层转化为金属硅化物层。该转化步骤包括在对流或传导装置中将金属层暴露于惰性传热气体（例如氩气，氮气）。

34. 发明申请

US20160293484A1 METHODS OF FORMING WIRING STRUCTURES 有权
标题翻译：形成接线结构的方法
公开(公告)号：US20160293484A1
公开(公告)日：2016-10-06
申请号：US15000302
申请日：2016-01-19
申请人： Jong-Jin Lee , Rak-Hwan Kim , Byung-Hee Kim , Jin-Nam Kim , Tsukasa Matsuda , Wan-Soo Park , Nae-In Lee , Jae-Won Chang , Eun-Ji Jung , Jeong-Ok Cha , Jae-Won Hwang , Jung-Ha Hwang
发明人： Jong-Jin Lee , Rak-Hwan Kim , Byung-Hee Kim , Jin-Nam Kim , Tsukasa Matsuda , Wan-Soo Park , Nae-In Lee , Jae-Won Chang , Eun-Ji Jung , Jeong-Ok Cha , Jae-Won Hwang , Jung-Ha Hwang
IPC分类号： H01L21/768
CPC分类号： H01L21/76882 , H01L21/76807 , H01L21/76843 , H01L21/76864 , H01L21/76877 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L23/53238
摘要： In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
摘要翻译：在形成布线结构的方法中，在基板上形成下部结构。在下部结构上形成绝缘中间层。部分去除绝缘中间层以形成至少一个通孔和虚拟通孔。绝缘中间层的上部被部分地去除以形成连接通孔和虚拟通孔的沟槽。形成填充通孔和虚拟通孔的第一金属层。填充沟槽的第二金属层形成在第一金属层上。

35. 发明申请

US20110189846A1 METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20110189846A1
公开(公告)日：2011-08-04
申请号：US13020979
申请日：2011-02-04
申请人： Jeong Gil Lee , Chang-Won Lee , Sang-Woo Lee , Sun-Woo Lee , Ki-Hyun Hwang , Jae-Hwa Park , Eun-Ji Jung
发明人： Jeong Gil Lee , Chang-Won Lee , Sang-Woo Lee , Sun-Woo Lee , Ki-Hyun Hwang , Jae-Hwa Park , Eun-Ji Jung
IPC分类号： H01L21/28
CPC分类号： H01L21/28
摘要： A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.
摘要翻译：公开了一种在半导体层上制造包括隧道氧化物层，初电电荷存储层和电介质层的非易失性存储器件的方法。在介电层上形成第一多晶硅层。在第一多晶硅层上形成阻挡层和第二多晶硅层。对第二多晶硅层，势垒层，第一多晶硅层，电介质层，初电电荷存储层和隧道氧化物层进行图案化以形成隧道层图案，电荷存储层图案，介电层图案，第一控制栅极图案，势垒层图案和第二多晶硅图案。在第二多晶硅层上形成镍层。对第二多晶硅图案和镍层进行热处理，以在阻挡层图案上形成包括NiSi的第二控制栅极图案。

36. 发明申请

US20080211039A1 Nonvolatile memory devices having metal silicide nanocrystals, methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices having metal silicide nanocrystals 审中-公开
标题翻译：具有金属硅化物纳米晶体的非易失性存储器件，形成金属硅化物纳米晶体的方法以及形成具有金属硅化物纳米晶体的非易失性存储器件的方法
公开(公告)号：US20080211039A1
公开(公告)日：2008-09-04
申请号：US11999704
申请日：2007-12-06
申请人： Xiaofeng Wang , Eun-Ji Jung , In-Seok Yeo
发明人： Xiaofeng Wang , Eun-Ji Jung , In-Seok Yeo
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L29/7881 , B82Y10/00 , H01L29/40114 , H01L29/42332 , H01L29/66825 , H01L29/7833
摘要： A nonvolatile memory device includes a semiconductor substrate. A charge storage insulating film containing metal silicide nanocrystals is on the substrate. A gate electrode is on the charge storage insulating film. Related methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices including metal silicide nanocrystals, are also disclosed.
摘要翻译：非易失性存储器件包括半导体衬底。含有金属硅化物纳米晶体的电荷存储绝缘膜位于基板上。栅电极位于电荷存储绝缘膜上。还公开了形成金属硅化物纳米晶体的相关方法，以及形成包括金属硅化物纳米晶体的非易失性存储器件的方法。

37. 发明申请

US20130020719A1 MICROELECTRONIC DEVICES INCLUDING THROUGH SILICON VIA STRUCTURES HAVING POROUS LAYERS 审中-公开
标题翻译：包含多孔硅的微电子器件通过具有多孔层的结构
公开(公告)号：US20130020719A1
公开(公告)日：2013-01-24
申请号：US13421388
申请日：2012-03-15
申请人： Eun-Ji Jung , Tsukasa Matsuda , Jongho Yun , Jongjin Lee , Gilheyun Choi , Seung-Wook Choi
发明人： Eun-Ji Jung , Tsukasa Matsuda , Jongho Yun , Jongjin Lee , Gilheyun Choi , Seung-Wook Choi
IPC分类号： H01L23/498
CPC分类号： H01L23/481 , H01L21/7682 , H01L21/76831 , H01L21/76898 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/00
摘要： A microelectronic device includes a substrate including a via hole extending therethrough, a porous layer on sidewalls of the via hole, and a conductive via electrode extending through the via hole between the sidewalls thereof. The porous layer includes a plurality of pores therein that reduce a dielectric constant of the porous layer. Related fabrication methods are also discussed.
摘要翻译：微电子器件包括：衬底，其包括贯穿其中的通孔，在通孔的侧壁上的多孔层，以及延伸通过其侧壁之间的通孔的导电通孔电极。多孔层包括其中的多个孔，其减小多孔层的介电常数。还讨论了相关的制造方法。

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