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31. 发明授权

US07183758B2 Automatic exchange of degraders in accelerated testing of computer chips 失效
标题翻译：自动交换降解器加速电脑芯片测试
公开(公告)号：US07183758B2
公开(公告)日：2007-02-27
申请号：US10734694
申请日：2003-12-12
申请人： Carl E. Bohnenkamp , Ethan H. Cannon , Ethan W. Cascio , Michael S. Gordon , Kenneth P. Rodbell , Theodore H. Zabel
发明人： Carl E. Bohnenkamp , Ethan H. Cannon , Ethan W. Cascio , Michael S. Gordon , Kenneth P. Rodbell , Theodore H. Zabel
IPC分类号： G01R31/28
CPC分类号： H01L21/68764 , H01L21/67213 , H01L21/68771
摘要： Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam stability if the accelerator can be left running continuously; and in-situ monitoring of beam current, beam position and stability. Particularly contemplated are methods and arrangements for changing degraders automatically, not manually, and in a safe manner.
摘要翻译：根据本发明的至少一个目前优选的实施例解决的问题是：在物理交换降解器（先前由手工完成）所花费的时间上的改进; 这样做的安全性，因为降解物变得高度放射性; 如果加速器可以连续运行，可能改善能量分辨率和光束稳定性; 并对射束电流，光束位置和稳定性进行现场监测。特别考虑的是自动而不是手动地以安全的方式改变降解器的方法和装置。

32. 发明授权

US08138573B2 On-chip heater and methods for fabrication thereof and use thereof 有权
标题翻译：片上加热器及其制造方法及其应用
公开(公告)号：US08138573B2
公开(公告)日：2012-03-20
申请号：US12766342
申请日：2010-04-23
申请人： Ethan H. Cannon , Alvin W. Strong
发明人： Ethan H. Cannon , Alvin W. Strong
IPC分类号： H01L31/115
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.
摘要翻译：片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。

33. 发明授权

US08133772B2 Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
标题翻译：用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
公开(公告)号：US08133772B2
公开(公告)日：2012-03-13
申请号：US13075271
申请日：2011-03-30
申请人： John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
发明人： John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

34. 发明申请

US20110309856A1 METHOD AND APPARATUS FOR REDUCING RADIATION AND CROSS-TALK INDUCED DATA ERRORS 有权
公开(公告)号：US20110309856A1
公开(公告)日：2011-12-22
申请号：US13015331
申请日：2011-01-27
申请人： Manuel F. Cabanas-Holmen , Ethan H. Cannon , Salim A. Rabaa
发明人： Manuel F. Cabanas-Holmen , Ethan H. Cannon , Salim A. Rabaa
IPC分类号： H03K19/003 , G06F17/50
CPC分类号： G11C5/005 , G11C7/02 , H03K3/0375 , H03K3/356121 , H03K17/693
摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

35. 发明授权

US07943482B2 Method for semiconductor device having radiation hardened insulators and design structure thereof 有权
标题翻译：具有辐射硬化绝缘体的半导体器件及其设计结构的方法
公开(公告)号：US07943482B2
公开(公告)日：2011-05-17
申请号：US12186762
申请日：2008-08-06
申请人： John M. Aitken , Ethan H. Cannon
发明人： John M. Aitken , Ethan H. Cannon
IPC分类号： H01L21/76 , G06F17/50
CPC分类号： H01L23/556 , H01L21/76283 , H01L23/481 , H01L23/585 , H01L24/24 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/14 , H01L2924/00
摘要： A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure includes: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.
摘要翻译：提供了一种在SOI技术中具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的设计结构。该装置包括第一结构和第二结构。第一结构包括：有源器件层下方的辐射硬化BOX层; 在有源器件层的有源区和辐射硬化BOX层之上的辐射硬化浅沟槽隔离（STI）结构; 在有源区域的栅极结构之上的一个或多个层间电介质层中的金属互连。第二结构被结合到第一结构。第二结构包括：基于硅的衬底; 衬底上的BOX层; BOX上有活性区的Si层; 在Si层的有源区之间的氧化物填充的STI结构; 以及栅极结构之上的一个或多个层间电介质层中的金属互连。至少一个金属互连件将第一结构电连接到第二结构。

36. 发明授权

US07881135B2 Method for QCRIT measurement in bulk CMOS using a switched capacitor circuit 有权
标题翻译：使用开关电容电路的批量CMOS QCRIT测量方法
公开(公告)号：US07881135B2
公开(公告)日：2011-02-01
申请号：US11679406
申请日：2007-02-27
申请人： Ethan H. Cannon , Alan J. Drake , Fadi H. Gebara , John P. Keane , AJ Kleinosowski
发明人： Ethan H. Cannon , Alan J. Drake , Fadi H. Gebara , John P. Keane , AJ Kleinosowski
IPC分类号： G11C29/00
CPC分类号： G01R31/318594 , G01R31/318597
摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.
摘要翻译：用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。电压测量电路测量电荷注入前后电荷注入电路中的电压。当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。

37. 发明授权

US07875854B2 Design structure for alpha particle sensor in SOI technology and structure thereof 有权
标题翻译： SOI技术中α粒子传感器的设计结构及其结构
公开(公告)号：US07875854B2
公开(公告)日：2011-01-25
申请号：US12099307
申请日：2008-04-08
申请人： Ethan H. Cannon , Michael J. Hauser , Timothy D. Sullivan
发明人： Ethan H. Cannon , Michael J. Hauser , Timothy D. Sullivan
IPC分类号： G01T1/178
CPC分类号： H01L31/115
摘要： The invention relates to a design structure, and more particularly, to a design structure for an alpha particle sensor in SOI technology and a circuit thereof. The structure is a silicon-on-insulator radiation detector which includes: a charge collection node; a precharge transistor that has a source from the charge collection node, a drain at Vdd, and a gate controlled by a precharge signal; an access transistor that has a source from the charge collection node, a drain connecting to a readout node, and a gate controlled by a read-out signal; and a detector pulldown transistor having a drain from the charge collection node, a source to ground, and a grounded gate.
摘要翻译：本发明涉及一种设计结构，更具体地说，涉及SOI技术中的α粒子传感器及其电路的设计结构。该结构是绝缘体上硅辐射检测器，其包括：电荷收集节点; 具有来自电荷收集节点的源极，Vdd处的漏极和由预充电信号控制的栅极的预充电晶体管; 具有来自电荷收集节点的源极，与读出节点连接的漏极和由读出信号控制的栅极的存取晶体管; 以及检测器下拉晶体管，其具有来自电荷收集节点的漏极，源极接地和接地栅极。

38. 发明授权

US07791169B2 Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors 失效
标题翻译： SOI CMOS技术的掩埋氧化物之下的电容器，用于防止软错误
公开(公告)号：US07791169B2
公开(公告)日：2010-09-07
申请号：US12105395
申请日：2008-04-18
申请人： John M. Aitken , Ethan H. Cannon , Philip J. Oldiges , Alvin W. Strong
发明人： John M. Aitken , Ethan H. Cannon , Philip J. Oldiges , Alvin W. Strong
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L29/92
摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
摘要翻译：公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。所形成的第一体层的隔离部分限定第一电容器板。与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

39. 发明授权

US07719887B2 CMOS storage devices configurable in high performance mode or radiation tolerant mode 有权
标题翻译： CMOS存储设备可在高性能模式或辐射容忍模式下配置
公开(公告)号：US07719887B2
公开(公告)日：2010-05-18
申请号：US11845170
申请日：2007-08-27
申请人： Ethan H. Cannon , Michael S. Gordon , Christopher D. LeBlanc , Kenneth P. Rodbell
发明人： Ethan H. Cannon , Michael S. Gordon , Christopher D. LeBlanc , Kenneth P. Rodbell
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C13/0004
摘要： A radiation tolerant circuit, structure of the circuit and method of autonomic radiation event device protection. The circuit includes a charge storage node connected to a resistor, the resistor comprising a material having an amorphous state and a crystalline state, the amorphous state having a higher resistance than the crystalline state, the material reversibly convertible between the amorphous state and the crystalline state by application of heat; an optional resistive heating element proximate to the resistor; and means for writing data to the charge storage node and means for reading data from the charge storage node.
摘要翻译：辐射耐受电路，电路结构及自主辐射事件装置保护方法。电路包括连接到电阻器的电荷存储节点，该电阻器包括具有非晶状态和结晶状态的材料，非晶状态具有比结晶状态更高的电阻，该材料可在非晶状态和结晶态之间可逆地转换通过应用热量; 靠近电阻器的可选电阻加热元件; 以及用于向电荷存储节点写入数据的装置和用于从电荷存储节点读取数据的装置。

40. 发明授权

US07704847B2 On-chip heater and methods for fabrication thereof and use thereof 失效
标题翻译：片上加热器及其制造方法及其应用
公开(公告)号：US07704847B2
公开(公告)日：2010-04-27
申请号：US11419341
申请日：2006-05-19
申请人： Ethan H. Cannon , Alvin W. Strong
发明人： Ethan H. Cannon , Alvin W. Strong
IPC分类号： H01L21/762
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.
摘要翻译：片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。

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