专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06765813B2 Integrated systems using vertically-stacked three-dimensional memory cells 有权
标题翻译：使用垂直堆叠的三维存储单元的集成系统
公开(公告)号：US06765813B2
公开(公告)日：2004-07-20
申请号：US10185588
申请日：2002-06-27
申请人： Roy E. Scheuerlein , J. James Tringali , Colm P. Lysaght , Alper Ilkbahar , Christopher S. Moore , David R. Friedman
发明人： Roy E. Scheuerlein , J. James Tringali , Colm P. Lysaght , Alper Ilkbahar , Christopher S. Moore , David R. Friedman
IPC分类号： G11C502
CPC分类号： G11C5/025 , G11C5/063 , G11C2213/71
摘要： Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：用于三维存储器阵列的支持电路至少部分地在三维存储器阵列的下方形成在衬底中，并且在三维存储器阵列下的衬底中限定开放区域。在一个优选实施例中，至少部分地在三维存储器阵列下的开放区域中形成一个或多个存储器阵列，而在另一个优选实施例中，实现一个或多个功能的逻辑电路至少部分地形成在开放区域三维记忆阵列。在另一优选实施例中，一个或多个存储器阵列和逻辑电路至少部分地形成在三维存储器阵列下方的开放区域中。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

32. 发明授权

US06470483B1 Method and apparatus for measuring internal clock skew 有权
标题翻译：用于测量内部时钟偏移的方法和装置
公开(公告)号：US06470483B1
公开(公告)日：2002-10-22
申请号：US09475443
申请日：1999-12-30
申请人： Pablo M. Rodriguez , Alper Ilkbahar
发明人： Pablo M. Rodriguez , Alper Ilkbahar
IPC分类号： G06F1750
CPC分类号： G01R31/318594 , G01R31/3016 , G01R31/31725 , G01R31/31858
摘要： An integrated circuit for measuring internal clock skew is provided. The integrated circuit includes a first controlled delay module, which is operable to receive one of a sampling clock signal and a sampled clock signal. The integrated circuit further includes a first flip-flop having a first input coupled to the first controlled delay module and a second input coupled to one of the sampling clock signal and said sampled clock signal. The first flip-flop is operable to generate an output based on skew between the sampled clock signal and the sampling clock signal.
摘要翻译：提供了一种用于测量内部时钟偏移的集成电路。集成电路包括第一受控延迟模块，其可操作以接收采样时钟信号和采样时钟信号之一。集成电路还包括第一触发器，其具有耦合到第一受控延迟模块的第一输入和耦合到采样时钟信号和所述采样时钟信号之一的第二输入。第一触发器可操作以基于采样时钟信号和采样时钟信号之间的偏差产生输出。

33. 发明授权

US06448824B1 Method and apparatus for integrated circuit power up 有权
标题翻译：用于集成电路供电的方法和装置
公开(公告)号：US06448824B1
公开(公告)日：2002-09-10
申请号：US09676728
申请日：2000-09-29
申请人： Pablo M. Rodriguez , Alper Ilkbahar
发明人： Pablo M. Rodriguez , Alper Ilkbahar
IPC分类号： H03K5153
CPC分类号： H03K17/223 , H03K17/302
摘要： A circuit to detect predetermined power supply levels so that sufficient power is provided for an integrated circuit to function properly and drive a bus. A first circuit indicates whether a first voltage has reached a first level, a second circuit indicates whether a second voltage has reached a second level, and a third circuit causes the second circuit to operate in a low power mode when the second voltage has reached a predetermined level. The first voltage is provided by an I/O power supply and the second voltage is provided by a core power supply.
摘要翻译：用于检测预定电源电平的电路，使得为集成电路提供足够的功率以正常工作并驱动总线。第一电路指示第一电压是否达到第一电平，第二电路指示第二电压是否已经达到第二电平，并且当第二电压达到第二电压时，第三电路使第二电路以低功率模式工作预定水平。第一电压由I / O电源提供，第二电压由核心电源提供。

34. 发明授权

US06433600B1 Method and apparatus for glitch protection for input buffers in a source-synchronous environment 有权
公开(公告)号：US06433600B1
公开(公告)日：2002-08-13
申请号：US09452885
申请日：1999-12-01
申请人： Alper Ilkbahar
发明人： Alper Ilkbahar
IPC分类号： H03K302
摘要： A method and apparatus for glitch protection for differential strobe input buffers in a source-synchronous environment. The present invention provides a solution to the problem of noise sensitivity of differential strobe input buffers in a source-synchronous environment, which may cause functional problems. The present invention enables the use of fully differential strobe signals to improve electrical performance of the source synchronous data transfers while removing the noise sensitivity problem associated with these signals. This is accomplished by providing a glitch protection circuit that provides protection against input glitches for a first predetermined period of time after each strobe transition. The present invention also provides a detection circuit that detects when both differential strobe signals are in the same logic state, which corresponds to a transition between bus masters (a dead cycle). The detection circuit causes the glitch protection circuit to latch the output signal of the glitch detection circuit.

35. 发明授权

US6154498A Computer system with a semi-differential bus signaling scheme 失效
标题翻译：具有半差分总线信令方案的计算机系统
公开(公告)号：US6154498A
公开(公告)日：2000-11-28
申请号：US938359
申请日：1997-09-26
申请人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
发明人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
IPC分类号： G06F13/40 , H04L25/06 , H04L25/08 , H04B3/00 , H03K3/00 , H04L23/00 , H04L27/00
CPC分类号： G06F13/4072 , H04L25/06 , H04L25/085
摘要： A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.
摘要翻译：描述了具有半差分总线信令方案的计算机系统。计算机系统包括耦合到公共总线的发射器。发射机将时钟信号和数据信号发送到接收机内的逻辑比较装置。逻辑比较器件将数据信号与参考电压进行比较，同时将时钟信号彼此进行比较。比较后，可以使用时钟信号将数据捕获到重新定时电路中。

36. 发明授权

US08637870B2 Three-dimensional memory device incorporating segmented array line memory array 有权
标题翻译：三维存储器件结合分段阵列线存储器阵列
公开(公告)号：US08637870B2
公开(公告)日：2014-01-28
申请号：US13348336
申请日：2012-01-11
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

37. 发明申请

US20120119178A1 MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME 有权
标题翻译：包含基于碳的存储元件的存储器单元及其形成方法
公开(公告)号：US20120119178A1
公开(公告)日：2012-05-17
申请号：US13351468
申请日：2012-01-17
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了形成金属 - 绝缘体 - 金属叠层的方法。该方法包括形成第一导电层，在第一导电层上形成电阻率切换碳基材料，并在碳基材料上形成第二导电层，其中碳基材料的厚度不大于十个原子层。还描述了其他方面。

38. 发明申请

US20070291563A1 Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information 失效
标题翻译：通过保证冗余信息的健康来提高半导体器件产量的方法和装置
公开(公告)号：US20070291563A1
公开(公告)日：2007-12-20
申请号：US11894861
申请日：2007-08-21
申请人： Alper Ilkbahar , Derek Bosch
发明人： Alper Ilkbahar , Derek Bosch
IPC分类号： G11C29/04
CPC分类号： G11C29/76
摘要： A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.
摘要翻译：提供了一种方法，其包括：读取一组存储器单元，指示存储的冗余信息是否可靠;以及如果存储单元组指示所存储的冗余信息是可靠的，则基于所存储的冗余信息确定是否读取主存储器还是冗余存储器。提供了另一种方法，包括读取与主存储器中的一组存储器单元相关联的一组存储器单元，该组存储器单元指示数据是否可以可靠地存储在存储器单元组中; 如果存储器单元组指示数据可以可靠地存储在存储器单元组中，则将数据存储在存储单元组中; 并且如果存储器单元组不指示数据可以可靠地存储在存储器单元组中，则将数据存储在冗余存储器中的一组存储器单元中。在另一个优选实施例中，提供了一种用于提供存储器冗余的方法。

39. 发明授权

US06453373B1 Method and apparatus for differential strobing 有权
标题翻译：差分选通方法和装置
公开(公告)号：US06453373B1
公开(公告)日：2002-09-17
申请号：US09475985
申请日：1999-12-30
申请人： Pablo M. Rodriguez , Alper Ilkbahar
发明人： Pablo M. Rodriguez , Alper Ilkbahar
IPC分类号： G06F1314
CPC分类号： G06F13/4213
摘要： A method for ensuring proper strobe pre and post driving between a first data transfer and a second data transfer in a microprocessor system. The method includes generating a first strobe signal and a second strobe signal, pre-driving one of said first and second strobe signals before the first data transfer, post driving said pre-driven signal, determining which of said first and second strobe signals will be post driven, and pre-driving one of said first and second strobe signals before the second data transfer.
摘要翻译：一种用于确保在微处理器系统中的第一数据传送和第二数据传送之间的适当的频闪前馈和后置驱动的方法。该方法包括产生第一选通信号和第二选通信号，在第一数据传输之前预驱动所述第一和第二选通信号之一，后驱动所述预驱动信号，确定所述第一和第二选通信号中的哪一个将是在第二数据传送之前，先驱动和预驱动所述第一和第二选通信号之一。

40. 发明授权

US06366867B2 Method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit 有权
标题翻译：为可补偿的驱动器电路提供可控制的补偿因子的方法和装置，其可以用于对经补偿的驱动器电路的结构完整性进行测试
公开(公告)号：US06366867B2
公开(公告)日：2002-04-02
申请号：US09337568
申请日：1999-06-22
申请人： Christopher John Sine , Alper Ilkbahar , Scott W. Murray
发明人： Christopher John Sine , Alper Ilkbahar , Scott W. Murray
IPC分类号： H03K1716
CPC分类号： G01R31/3185 , G01R31/30 , G01R31/31715 , H03K19/018585
摘要： A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit. One disclosed apparatus includes a compensated driver circuit having a number of subcomponents. At least one compensation factor, which may be provided by a compensation circuit, controls which of the subcomponents to enable. An additional circuit is coupled to provide controllable values for the at least one compensation factor.
摘要翻译：一种用于向经补偿的驱动器电路提供可控补偿因子的方法和装置，其可用于对经补偿的驱动器电路的结构完整性进行测试。一种公开的装置包括具有多个子部件的补偿驱动器电路。可以由补偿电路提供的至少一个补偿因子控制哪些子部件能够实现。耦合附加电路以为至少一个补偿因子提供可控制的值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式