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1. 发明授权

US08065576B2 Test access port 有权
标题翻译：测试访问端口
公开(公告)号：US08065576B2
公开(公告)日：2011-11-22
申请号：US12611775
申请日：2009-11-03
申请人： David E. Miner , Steven J. Tu , Scott W. Murray
发明人： David E. Miner , Steven J. Tu , Scott W. Murray
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318552
摘要： A semiconductor chip is described having a plurality of processing cores. The semiconductor chip also includes a plurality of test controllers. Each test controller is associated with a different one of the processing cores. The semiconductor chip also includes a test port having a first serial input and a first serial output. The first serial input is to receive serial test input data provided to the semiconductor chip. The first serial output is to provide serial output data provided by the semiconductor chip. The semiconductor chip further includes switch circuitry coupled to the test port and the plurality of test controllers. The switch circuitry is to route the serial test input data to one of the plurality of test controllers and to route the serial output data from one of the plurality of test controllers to the first serial output. The semiconductor chip further includes a configuration register coupled to the switch circuitry to establish the switch circuitry's routing configuration.
摘要翻译：描述了具有多个处理核心的半导体芯片。半导体芯片还包括多个测试控制器。每个测试控制器与不同的处理核心相关联。半导体芯片还包括具有第一串行输入和第一串行输出的测试端口。第一个串行输入是接收提供给半导体芯片的串行测试输入数据。第一个串行输出是提供由半导体芯片提供的串行输出数据。半导体芯片还包括耦合到测试端口和多个测试控制器的开关电路。开关电路将串行测试输入数据路由到多个测试控制器中的一个，并将串行输出数据从多个测试控制器中的一个路由到第一串行输出。半导体芯片还包括配置寄存器，其配置到开关电路以建立开关电路的布线配置。

2. 发明授权

US07627797B2 Test access port 有权
标题翻译：测试访问端口
公开(公告)号：US07627797B2
公开(公告)日：2009-12-01
申请号：US11477837
申请日：2006-06-29
申请人： David E. Miner , Steven J. Tu , Scott W. Murray
发明人： David E. Miner , Steven J. Tu , Scott W. Murray
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318552
摘要： A method, apparatus, and system are provided for testing multi-core processors. The testing includes a test control mechanism and a multi-core processor including a set of cores with at least one core having a test access port controller (TAPC), distributed data, and a set of distributed control registers. The multi-core processor and the test control mechanism further having a configuration to provide testing the multi-core processor. The test control mechanism is modified to simultaneously test multiple cores.
摘要翻译：提供了一种用于测试多核处理器的方法，装置和系统。该测试包括一个测试控制机制和一个多核处理器，它包括一组具有至少一个具有测试访问端口控制器（TAPC），分布式数据和一组分布式控制寄存器的核心的核心。多核处理器和测试控制机构还具有提供对多核处理器的测试的配置。修改测试控制机制，同时测试多个核心。

3. 发明申请

US20100050019A1 TEST ACCESS PORT 有权
标题翻译：测试访问端口
公开(公告)号：US20100050019A1
公开(公告)日：2010-02-25
申请号：US12611775
申请日：2009-11-03
申请人： David E. Miner , Steven J. Tu , Scott W. Murray
发明人： David E. Miner , Steven J. Tu , Scott W. Murray
IPC分类号： G06F11/273
CPC分类号： G06F11/267 , G01R31/318552
摘要： Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.
摘要翻译：简而言之，根据本发明的实施例的描述，用于多核处理器的测试访问端口。

4. 发明授权

US06366867B2 Method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit 有权
标题翻译：为可补偿的驱动器电路提供可控制的补偿因子的方法和装置，其可以用于对经补偿的驱动器电路的结构完整性进行测试
公开(公告)号：US06366867B2
公开(公告)日：2002-04-02
申请号：US09337568
申请日：1999-06-22
申请人： Christopher John Sine , Alper Ilkbahar , Scott W. Murray
发明人： Christopher John Sine , Alper Ilkbahar , Scott W. Murray
IPC分类号： H03K1716
CPC分类号： G01R31/3185 , G01R31/30 , G01R31/31715 , H03K19/018585
摘要： A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit. One disclosed apparatus includes a compensated driver circuit having a number of subcomponents. At least one compensation factor, which may be provided by a compensation circuit, controls which of the subcomponents to enable. An additional circuit is coupled to provide controllable values for the at least one compensation factor.
摘要翻译：一种用于向经补偿的驱动器电路提供可控补偿因子的方法和装置，其可用于对经补偿的驱动器电路的结构完整性进行测试。一种公开的装置包括具有多个子部件的补偿驱动器电路。可以由补偿电路提供的至少一个补偿因子控制哪些子部件能够实现。耦合附加电路以为至少一个补偿因子提供可控制的值。

5. 发明授权

US07139947B2 Test access port 有权
公开(公告)号：US07139947B2
公开(公告)日：2006-11-21
申请号：US09746676
申请日：2000-12-22
申请人： David E. Miner , Steven J. Tu , Scott W. Murray
发明人： David E. Miner , Steven J. Tu , Scott W. Murray
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318552
摘要： Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

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