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31. 发明授权

US5578852A Semiconductor memory cell having information storage transistor and switching transistor 失效
公开(公告)号：US5578852A
公开(公告)日：1996-11-26
申请号：US541127
申请日：1995-10-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L27/01 , H01L27/12 , H01L29/76 , H01L31/0392
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.

32. 发明授权

US5576571A Semiconductor memory cell having information storage transistor and switching transistor 失效
标题翻译：具有信息存储晶体管和开关晶体管的半导体存储单元
公开(公告)号：US5576571A
公开(公告)日：1996-11-19
申请号：US541173
申请日：1995-10-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.1, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.
摘要翻译：提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许短通道设计，并且可以减小单元格区域。半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L1，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L2连接到固定电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

33. 发明授权

US5506436A Semiconductor memory cell 失效
标题翻译：半导体存储单元
公开(公告)号：US5506436A
公开(公告)日：1996-04-09
申请号：US420068
申请日：1995-04-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L27/01 , H01L29/76
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub. 2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.
摘要翻译：提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许短通道设计，并且可以减小单元格区域。半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L3，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L 2连接到固定电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

34. 外观设计

USD364634S 35 MM camera 失效
公开(公告)号：USD364634S
公开(公告)日：1995-11-28
申请号：US32879
申请日：1994-12-30
申请人： Takeshi Matsushita
设计人： Takeshi Matsushita

35. 发明授权

US5427973A Method for production of SOI transistor device having a storage cell 失效
标题翻译：具有存储单元的SOI晶体管器件的制造方法
公开(公告)号：US5427973A
公开(公告)日：1995-06-27
申请号：US230713
申请日：1994-04-21
申请人： Hiroshi Satoh , Yasunori Ohokubo , Takeshi Matsushita , Toshiyuki Nishihara , Makoto Hashimoto
发明人： Hiroshi Satoh , Yasunori Ohokubo , Takeshi Matsushita , Toshiyuki Nishihara , Makoto Hashimoto
IPC分类号： H01L29/772 , H01L21/762 , H01L23/544 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L23/544 , H01L21/76251 , H01L27/1082 , H01L27/10832 , H01L2223/54453 , H01L2924/0002 , Y10S148/012 , Y10S438/975 , Y10S438/977
摘要： A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique storage node having a conductive side wall.
摘要翻译：一种用于形成SOI结构的晶片接合方法，包括以下步骤：使晶片在与一个晶片的状态相接近的状态下与另一个晶片略微，基本上均匀的间隙，并将两个晶片的至少一个晶片的一个点压在另一个晶片上晶圆。在本发明的另一方面，提供了一种使用在SOI衬底上形成的对准标记部分和/或游标部分进行光刻定位的方法，其包括以下步骤：去除对准标记部分对应的半导体层部分和/ 或游标部分。在本发明的另一方面，提供了一种通过使用SOI结构形成的新的DRAM半导体器件，其包括沿字线纵向形成的栅格节点的新图案。此外，提供了通过使用SOI结构形成的新的DRAM半导体器件，其包括具有导电侧壁的唯一存储节点。

36. 发明授权

US5102819A Method of making a DRAM cell 失效
标题翻译：制造DRAM单元的方法
公开(公告)号：US5102819A
公开(公告)日：1992-04-07
申请号：US644448
申请日：1991-01-23
申请人： Takeshi Matsushita , Muneharu Shimanoe , Hiroshi Sato , Akira Nieda
发明人： Takeshi Matsushita , Muneharu Shimanoe , Hiroshi Sato , Akira Nieda
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/1082 , H01L27/10832
摘要： A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate. The method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions in recesses formed by the insulating layer. The lapping process uses an alkaline liquid as a lapping liquid and employs a lapping disk provided with a hard lapping pad to finish the surfaces of the semiconductor regions flush with the surface of the insulating layer by lapping.

37. 发明授权

US4980308A Method of making a thin film transistor 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US4980308A
公开(公告)日：1990-12-25
申请号：US433449
申请日：1989-11-13
申请人： Hisao Hayashi , Takeshi Matsushita
发明人： Hisao Hayashi , Takeshi Matsushita
IPC分类号： H01L27/00 , H01L21/02 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L23/528 , H01L27/088 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L21/768 , H01L23/5283 , H01L2924/0002 , Y10S438/928 , Y10S438/977
摘要： The present invention relates to a semiconductor device in which a semiconductor element is formed on a semiconductor layer (3) supported on a substrate (1) via at least insulating layers (2) and (4) as shown in FIGS. 1 and 2 and a method of fabricating the same. The semiconductor layer (3) has wiring layers (5) and (6) on both surfaces thereof, thus leading itself well for increasing the density of wiring and for increasing the operation speed in a large-scale integrated circuit device.
摘要翻译：本发明涉及半导体器件，其中半导体元件至少通过绝缘层（2）和（4）形成在支撑在基底（1）上的半导体层（3）上，如图1和2所示。 1和2及其制造方法。半导体层（3）的两面具有布线层（5）和（6），因此能够很好地提高布线的密度，提高大型集成电路装置的运行速度。

38. 发明授权

US4063275A Semiconductor device with two passivating layers 失效
标题翻译：具有两个钝化层的半导体器件
公开(公告)号：US4063275A
公开(公告)日：1977-12-13
申请号：US624889
申请日：1975-10-22
申请人： Takeshi Matsushita , Hisao Hayashi , Teruaki Aoki , Hidenobu Mochizuki
发明人： Takeshi Matsushita , Hisao Hayashi , Teruaki Aoki , Hidenobu Mochizuki
IPC分类号： H01L21/322 , H01L21/314 , H01L21/331 , H01L21/8247 , H01L23/31 , H01L29/06 , H01L29/73 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/861 , H01L29/04 , H01L23/30
CPC分类号： H01L23/3192 , H01L21/314 , H01L23/3157 , H01L23/3171 , H01L2924/0002 , H01L2924/13091 , H01L2924/3025 , Y10S257/905
摘要： A semiconductive device is provided which includes a single crystal substrate. A first insulating layer arranged on one surface of the substrate is of polycrystalline silicon containing oxygen. A second insulating layer formed on the first insulating layer is of polycrystalline silicon containing one of a group consisting of nitrogen, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and silicone resin. The substrate includes at least one PN junction which extends to the said surface of the substrate. A novel method of making is also disclosed.
摘要翻译：提供了包括单晶衬底的半导体器件。布置在基板的一个表面上的第一绝缘层是含氧的多晶硅。形成在第一绝缘层上的第二绝缘层是由氮，Si 3 N 4，Al 2 O 3和有机硅树脂组成的组中的一种的多晶硅。衬底包括延伸到衬底的所述表面的至少一个PN结。还公开了一种新颖的制造方法。

39. 发明授权

US4062707A Utilizing multiple polycrystalline silicon masks for diffusion and passivation 失效
标题翻译：利用多个多晶硅掩模进行扩散和钝化
公开(公告)号：US4062707A
公开(公告)日：1977-12-13
申请号：US654598
申请日：1976-02-02
申请人： Hidenobu Mochizuki , Teruaki Aoki , Takeshi Matsushita , Hisao Hayashi , Masanori Okayama
发明人： Hidenobu Mochizuki , Teruaki Aoki , Takeshi Matsushita , Hisao Hayashi , Masanori Okayama
IPC分类号： H01L29/73 , H01L21/033 , H01L21/22 , H01L21/314 , H01L21/331 , H01L23/29 , H01L29/00 , H01L21/31
CPC分类号： H01L23/291 , H01L21/033 , H01L21/314 , H01L29/00 , H01L2924/0002 , H01L2924/13091 , Y10S438/945
摘要： A method for fabricating a semiconductor device includes the steps of forming a first polycrystalline silicon layer containing oxygen atoms on a semiconductor layer, of forming a second polycrystalline silicon layer containing nitrogen atoms on the first polycrystalline silicon layer, of removing a predetermined part of the first and second polycrystalline silicon layers to form an opening therein, and of diffusing impurity material into the semiconductor layer through the opening in order to form a diffused region. The fabricating process can be remarkably simplified.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体层上形成含有氧原子的第一多晶硅层，在第一多晶硅层上形成含氮原子的第二多晶硅层，去除第一多晶硅层的预定部分和第二多晶硅层，以在其中形成开口，并且通过开口将杂质材料扩散到半导体层中，以形成扩散区域。制造工艺可以非常简化。

40. 发明授权

US3990100A Semiconductor device having an antireflective coating 失效
标题翻译：具有抗反射涂层的半导体装置
公开(公告)号：US3990100A
公开(公告)日：1976-11-02
申请号：US619054
申请日：1975-10-02
申请人： Takayoshi Mamine , Takeshi Matsushita
发明人： Takayoshi Mamine , Takeshi Matsushita
IPC分类号： H01L31/04 , G02B1/11 , G02B1/113 , H01L21/314 , H01L31/02 , H01L31/0216 , H01L31/068 , H01L31/10 , H01L27/14
CPC分类号： H01L31/02168 , H01L31/02161 , Y02E10/50
摘要： A polycrystalline silicon layer provides an antireflective coating on a semiconductor surface of a photo-sensitive detector, the polycrystalline silicon layer containing from 25 to 45 atomic percent of oxygen and having a refractive index intermediate that of the semiconductor crystal and the exterior environment.
摘要翻译：多晶硅层在光敏检测器的半导体表面上提供抗反射涂层，该多晶硅层含有25至45原子％的氧并具有中间体半导体晶体和外部环境的折射率。

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