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1. 发明授权

US5437762A Method and apparatus for semiconductor memory 失效
标题翻译：半导体存储器的方法和装置
公开(公告)号：US5437762A
公开(公告)日：1995-08-01
申请号：US274587
申请日：1994-07-13
申请人： Akihiko Ochiai , Makoto Hashimoto , Takeshi Matsushita , Machio Yamagishi , Hiroshi Sato , Muneharu Shimanoe
发明人： Akihiko Ochiai , Makoto Hashimoto , Takeshi Matsushita , Machio Yamagishi , Hiroshi Sato , Muneharu Shimanoe
IPC分类号： H01L21/28 , H01L21/762 , H01L21/8247 , H01L21/84 , H01L21/306
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76264 , H01L21/84 , H01L21/76275 , H01L21/76283 , Y10S148/012 , Y10S148/135
摘要： The invention concerns a method of forming various kinds of SOI structures and semiconductor memory devices using the forming technique. It is useful, for example, in SRAM or EEPROM devices. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer. It includes a method of manufacturing a structure via the steps of forming an etching stopping layer on the surface of a silicon substrate, forming an epitaxially grown silicon layer on said etching stopping layer, bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, grinding said silicon substrate from the rear face and etching it until said etching stopping layer is exposed and removing said etching stopper layer, with or without polishing the other surface of said silicon substrate.
摘要翻译：本发明涉及使用成形技术形成各种SOI结构和半导体存储器件的方法。例如，在SRAM或EEPROM设备中是有用的。在EEPROM中，特别涉及一种制造非易失性存储器件的方法，其中控制栅电极层通过绝缘膜层叠在浮栅电极层上。它包括通过在硅衬底的表面上形成蚀刻停止层的步骤制造结构的方法，在所述蚀刻停止层上形成外延生长的硅层，将形成有所述硅层的硅衬底与另一个衬底接合作为绝缘体衬底，从后表面研磨所述硅衬底并对其进行蚀刻，直到所述蚀刻停止层露出，并且在所述硅衬底的另一表面上抛光或不抛光所述蚀刻停止层。

2. 发明授权

US5892256A Semiconductor memory and a method of manufacturing the same 失效
标题翻译：半导体存储器及其制造方法
公开(公告)号：US5892256A
公开(公告)日：1999-04-06
申请号：US804747
申请日：1997-02-21
申请人： Takeshi Matsushita , Muneharu Shimanoe , Hiroshi Sato , Akira Nieda
发明人： Takeshi Matsushita , Muneharu Shimanoe , Hiroshi Sato , Akira Nieda
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/1082 , H01L27/10832
摘要： A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate. The method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions in recesses formed by the insulating layer. The lapping process uses an alkaline liquid as a lapping liquid and employs a lapping disk provided with a hard lapping pad to finish the surfaces of the semiconductor regions flush with the surface of the insulating layer by lapping.
摘要翻译：一种具有由MIS晶体管和电容器组成的存储单元的半导体存储器及其制造方法。半导体存储器包括半导体衬底，形成在半导体衬底上的绝缘层和形成在绝缘层的表面上的半导体区域。半导体存储器的特征在于，MIS晶体管分别形成在半导体区域的表面上并且通过绝缘层彼此分离并且与半导体衬底分离，并且电容器分别形成在相应的MIS晶体管。将MIS晶体管彼此分开并从半导体衬底分离的绝缘层减少了存储单元之间的电流泄漏，并降低了在MIS晶体管和半导体衬底侧形成的位线之间的电容。半导体存储器的制造方法包括：在由绝缘层形成的凹部中形成半导体区域时研磨晶片的表面的研磨工艺。研磨过程使用碱性液体作为研磨液，并使用配有硬研磨垫的研磨盘，通过研磨完成与绝缘层表面齐平的半导体区域的表面。

3. 发明授权

US5102819A Method of making a DRAM cell 失效
标题翻译：制造DRAM单元的方法
公开(公告)号：US5102819A
公开(公告)日：1992-04-07
申请号：US644448
申请日：1991-01-23
申请人： Takeshi Matsushita , Muneharu Shimanoe , Hiroshi Sato , Akira Nieda
发明人： Takeshi Matsushita , Muneharu Shimanoe , Hiroshi Sato , Akira Nieda
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/1082 , H01L27/10832
摘要： A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate. The method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions in recesses formed by the insulating layer. The lapping process uses an alkaline liquid as a lapping liquid and employs a lapping disk provided with a hard lapping pad to finish the surfaces of the semiconductor regions flush with the surface of the insulating layer by lapping.

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