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1. 发明授权

US5581106A Semiconductor memory cell having information storage transistor and switching transistor 失效
公开(公告)号：US5581106A
公开(公告)日：1996-12-03
申请号：US541180
申请日：1995-10-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.

2. 发明授权

US5578853A Semiconductor memory cell having information storage transistor and switching transistor 失效
标题翻译：具有信息存储晶体管和开关晶体管的半导体存储单元
公开(公告)号：US5578853A
公开(公告)日：1996-11-26
申请号：US541172
申请日：1995-10-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L27/01 , H01L27/12 , H01L29/76 , H01L31/0392
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.
摘要翻译：提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许短通道设计，并且可以减小单元格区域。半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L3，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L2连接到固定电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

3. 发明授权

US5428238A Semiconductor memory cell having information storage transistor and switching transistor 失效
标题翻译：具有信息存储晶体管和开关晶体管的半导体存储单元
公开(公告)号：US5428238A
公开(公告)日：1995-06-27
申请号：US164812
申请日：1993-12-10
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L27/02 , H01L27/01 , H01L29/00
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.l and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub. 2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.
摘要翻译：提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许短通道设计，并且可以减小单元格区域。半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L3，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L 2连接到固定电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

4. 发明授权

US5578852A Semiconductor memory cell having information storage transistor and switching transistor 失效
公开(公告)号：US5578852A
公开(公告)日：1996-11-26
申请号：US541127
申请日：1995-10-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L27/01 , H01L27/12 , H01L29/76 , H01L31/0392
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.

5. 发明授权

US5576571A Semiconductor memory cell having information storage transistor and switching transistor 失效
标题翻译：具有信息存储晶体管和开关晶体管的半导体存储单元
公开(公告)号：US5576571A
公开(公告)日：1996-11-19
申请号：US541173
申请日：1995-10-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.1, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.
摘要翻译：提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许短通道设计，并且可以减小单元格区域。半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L1，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L2连接到固定电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

6. 发明授权

US5506436A Semiconductor memory cell 失效
标题翻译：半导体存储单元
公开(公告)号：US5506436A
公开(公告)日：1996-04-09
申请号：US420068
申请日：1995-04-11
申请人： Yutaka Hayashi , Takeshi Matsushita
发明人： Yutaka Hayashi , Takeshi Matsushita
IPC分类号： G11C11/405 , G11C11/404 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/786 , H01L27/01 , H01L29/76
CPC分类号： H01L27/108 , G11C11/404
摘要： A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub. 2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.
摘要翻译：提供了一种结构的半导体存储单元或用于ASIC的半导体存储单元，其确保稳定的晶体管操作，其不需要常规DRAM中所需的大容量电容器，这确保可靠地读取和写入信息，这允许短通道设计，并且可以减小单元格区域。半导体存储单元包括：包括半导体沟道层Ch1，第一和第二导电栅极G1，G2以及第一和第二导电层L1，L2的信息存储晶体管TR1; 以及包括半导体沟道形成区域Ch2，第三导电栅极G3以及第三和第四导电层L3，L4的开关晶体管TR2，其中第四导电层L4连接到第二导电栅极G2，第一导电栅极G1和第三导电栅极G3连接到第一存储单元选择线，第一导电层L1和第三导电层L3连接到第二存储单元选择线，第二导电层L 2连接到固定电位，并且半导体沟道形成区域Ch2连接到读/写选择线。

7. 发明申请

US20130224557A1 SEPARATOR FOR NON-AQUEOUS BATTERIES AND NON-AQUEOUS BATTERY EQUIPPED WITH SAME, AND PROCESS FOR MANUFACTURING SEPARATOR FOR NON-AQUEOUS BATTERIES 有权
标题翻译：非水性电池分离器和配备非水电池的非电池电池以及非水电池制造分离器的工艺
公开(公告)号：US20130224557A1
公开(公告)日：2013-08-29
申请号：US13881747
申请日：2011-10-13
申请人： Tomohiro Hayakawa , Takayoshi Hosoya , Hiroyuki Kawai , Hideo Hayashi , Yutaka Hayashi , Kohsuke Togashi , Naotaka Gotoh
发明人： Tomohiro Hayakawa , Takayoshi Hosoya , Hiroyuki Kawai , Hideo Hayashi , Yutaka Hayashi , Kohsuke Togashi , Naotaka Gotoh
IPC分类号： H01M2/16
CPC分类号： H01M2/1653 , C08G18/04 , C08G18/4009 , H01M2/162 , H01M2/1666 , H01M2/1686 , H01M10/052 , Y02E60/122 , Y02P70/54
摘要： Provided is a separator for non-aqueous batteries, capable of being usefully used in non-aqueous batteries, and a non-aqueous battery equipped with this separator. The separator for non-aqueous batteries includes: a base layer comprising a fiber aggregate, and an electrolyte-swellable resin layer formed on at least one surface of the base layer, the resin layer comprising a urethane resin (C) obtained by reacting a polyol (A) including a vinyl polymer (a1) and a polyether polyol (a2) with a polyisocyanate (B). The vinyl polymer (a1) has as a main chain a vinyl polymer (a1′) having two hydroxyl groups at one of the termini of the main chain, and a polyoxyethylene chain having a number average molecular weight of 200 to 800 as a side chain, the percentage of the polyoxyethylene chain based on the vinyl polymer (a1) being within the range of 70 mass % to 98 mass %.
摘要翻译：本发明提供一种能够用于非水电池的非水电池用隔膜，以及配备有该隔膜的非水电池。非水电池用隔膜包括：包含纤维聚集体的基层和形成在基层的至少一个表面上的电解质溶胀性树脂层，所述树脂层包含聚氨酯树脂（C），其通过使多元醇（A）包括乙烯基聚合物（a1）和聚醚多元醇（a2）与多异氰酸酯（B）。乙烯基聚合物（a1）作为主链具有在主链的一个末端具有两个羟基的乙烯基聚合物（a1'）和作为侧链的数均分子量为200〜800的聚氧乙烯链基于乙烯基聚合物（a1）的聚氧乙烯链的百分比在70质量％至98质量％的范围内。

8. 发明授权

US08450799B2 Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
公开(公告)号：US08450799B2
公开(公告)日：2013-05-28
申请号：US11975923
申请日：2007-10-22
申请人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
IPC分类号： H01L29/34
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

9. 发明授权

US08094484B2 Memory cell array 有权
标题翻译：存储单元阵列
公开(公告)号：US08094484B2
公开(公告)日：2012-01-10
申请号：US12644851
申请日：2009-12-22
申请人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
发明人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
IPC分类号： G11C11/00
CPC分类号： H01L27/24 , G11C13/00 , G11C13/0069 , G11C13/02 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.
摘要翻译：公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和门极阈值电压以下。

10. 发明申请

US20100208522A1 MEMORY DEVICE AND READING METHOD THEREOF 有权
标题翻译：存储器件及其读取方法
公开(公告)号：US20100208522A1
公开(公告)日：2010-08-19
申请号：US12601788
申请日：2008-05-23
申请人： Yutaka Hayashi , Kazuhika Matsumoto , Takafumi Kamimura
发明人： Yutaka Hayashi , Kazuhika Matsumoto , Takafumi Kamimura
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/0657 , H01L29/1606 , H01L29/42336 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/6684 , H01L29/7781 , H01L29/792
摘要： A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.
摘要翻译：存储器件（1）至少包括具有由第一表面包围的长度，第一表面和横截面的第一半导体区域（100），设置在第一表面上的存储器件（300）和栅极 400），并且将第一半导体区域（100）的横截面的等效截面半径设定为等于或小于存储装置（300）的等效氧化硅膜厚度，实现低编程电压。横截面的等效截面半径r设定为10nm以下，栅极长度设定为20nm以下，使得转换为栅极电压的多级间隔成为能够在室内识别的特定值温度。

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