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31. 发明申请

US20050280503A1 Semiconductor wafer having identification unit and method of identifying the semiconductor wafer using the identification unit 审中-公开
标题翻译：具有识别单元的半导体晶片和使用识别单元识别半导体晶片的方法
公开(公告)号：US20050280503A1
公开(公告)日：2005-12-22
申请号：US11147314
申请日：2005-06-08
申请人： Sang-Woo Lee , Cheol-Joon Yoo , Dong-Bin Kim
发明人： Sang-Woo Lee , Cheol-Joon Yoo , Dong-Bin Kim
IPC分类号： H01L21/02 , H01L23/544 , H04Q5/22
CPC分类号： H01L23/544 , H01L2223/54413 , H01L2223/54446 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer, comprising a radio frequency identification (RFID) chip on one side of the semiconductor wafer, on which a pattern has been formed, wherein information on the wafer is input to and/or output from the RFID chip using radio frequency communication.
摘要翻译：一种半导体晶片，包括在其上形成图案的半导体晶片的一侧上的射频识别（RFID）芯片，其中晶片上的信息被使用射频通信输入到和/或从RFID芯片输出。

32. 发明申请

US20050133563A1 Wire bonding apparatus and method for clamping a wire 有权
标题翻译：导线接合装置和夹紧线的方法
公开(公告)号：US20050133563A1
公开(公告)日：2005-06-23
申请号：US10928402
申请日：2004-08-30
申请人： Tae-Hyun Kim , Youn-Sung Ko , Young-Kyun Sun , Dae-Soo Kim , Kook-Jin Oh , Sang-Woo Lee , Dong-Bin Kim
发明人： Tae-Hyun Kim , Youn-Sung Ko , Young-Kyun Sun , Dae-Soo Kim , Kook-Jin Oh , Sang-Woo Lee , Dong-Bin Kim
IPC分类号： H01L21/60 , B23K20/00 , H01L21/607 , B23K37/00 , B23K1/06
CPC分类号： H01L24/85 , B23K20/004 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L2224/05553 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/48472 , H01L2224/49171 , H01L2224/78268 , H01L2224/78301 , H01L2224/786 , H01L2224/7865 , H01L2224/789 , H01L2224/78901 , H01L2224/85045 , H01L2224/851 , H01L2224/85181 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A controller may receive a wire disconnection signal from a wire bonding monitoring system and operate a wire clamp to clamp a disconnected wire. A series of operations, which may include a wire drawing operation, a wire tail forming operation and a ball forming operation, may be automatically performed. A sensor may measure the length of the wire drawn through the capillary and the location of a ball that may be formed at a wire tail. An auxiliary clamp may be installed between the wire clamp and the capillary for drawing the wire using sensor information.
摘要翻译：控制器可以从引线接合监测系统接收线断线信号，并且操作线夹以夹紧断开的线。可以自动执行一系列操作，其可以包括拉丝操作，线尾成型操作和滚珠成形操作。传感器可以测量通过毛细管拉出的丝的长度和可以形成在丝尾的球的位置。辅助夹具可以安装在线夹和毛细管之间，用于使用传感器信息绘制线。

33. 发明授权

US06909134B2 Ferroelectric memory device using via etch-stop layer and method for manufacturing the same 失效
标题翻译：使用通过蚀刻停止层的铁电存储器件及其制造方法
公开(公告)号：US06909134B2
公开(公告)日：2005-06-21
申请号：US10721689
申请日：2003-11-24
申请人： Yoon-Jong Song , Ki-Nam Kim , Sang-Woo Lee
发明人： Yoon-Jong Song , Ki-Nam Kim , Sang-Woo Lee
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L27/108
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.
摘要翻译：铁电存储器件及其制造方法。铁电存储器件包括形成在半导体衬底上的下层间绝缘层。铁电存储器件还包括设置在下层间绝缘层上的至少两个相邻的铁电电容器，形成在强电介质电容器上的层间绝缘层，留下暴露的铁电电容器的顶表面，形成在其上的图案化通孔蚀刻停止层层间绝缘层，使电容器的顶表面暴露，形成在图案化通孔蚀刻停止层上的上层间绝缘层，以及通常连接到至少两个相邻铁电电容器的板线。因此，可以显着增加铁电存储器件的集成。

34. 发明申请

US20050126696A1 Snap cure device for semiconductor chip attachment 审中-公开
标题翻译：用于半导体芯片连接的快速固化装置
公开(公告)号：US20050126696A1
公开(公告)日：2005-06-16
申请号：US10976790
申请日：2004-11-01
申请人： Kook-Jin Oh , Young-Han Kwon , Tae-Hyuk Kim , Suk-Chun Jung , Byung-Soo Kim , Sang-Woo Lee , Jung-Hyon Byon
发明人： Kook-Jin Oh , Young-Han Kwon , Tae-Hyuk Kim , Suk-Chun Jung , Byung-Soo Kim , Sang-Woo Lee , Jung-Hyon Byon
IPC分类号： H01L21/52 , H01L21/00 , H01L21/677 , B32B31/00 , H01L21/30 , H01L21/46
CPC分类号： H01L21/67754 , H01L21/67103
摘要： Provided are a variety of snap cure apparatus configuration and corresponding methods for operating each such apparatus in order to snap cure an adhesive composition. Each of the configurations includes at least one vertical stack of heater blocks whereby the horizontal area required for conducting the snap cure processing may be reduced. Depending on the configuration utilized, two or more transfer devices may be required to remove the substrate(s) from a conveyor, index the substrate(s) through the heater blocks to apply the predetermined thermal cycle and return the cured substrate to the conveyor. Similarly, depending on the particular adhesive utilized, the number, relative temperatures, and duration of the substrate(s) on each of the heater blocks may be adjusted to provide the desired degree of curing.
摘要翻译：提供了各种快速固化设备配置和用于操作每个这样的设备的相应方法，以便将粘合剂组合物快速固化。每个配置包括至少一个垂直堆叠的加热器块，由此可以减少用于进行快速固化处理所需的水平面积。根据所使用的配置，可能需要两个或更多个转移装置以从输送机移除基材，从而将基底指引通过加热器块以施加预定的热循环并将固化的基底返回到输送机。类似地，取决于所使用的具体粘合剂，可以调节每个加热器块上的基底的数量，相对温度和持续时间以提供所需的固化程度。

35. 发明申请

US20050086512A1 Worm blocking system and method using hardware-based pattern matching 审中-公开
标题翻译：蠕虫阻塞系统和方法采用基于硬件的模式匹配
公开(公告)号：US20050086512A1
公开(公告)日：2005-04-21
申请号：US10932063
申请日：2004-09-02
申请人： Sang-Woo Lee , Yeon-Sik Ryu , Seung-Jong Pyo
发明人： Sang-Woo Lee , Yeon-Sik Ryu , Seung-Jong Pyo
IPC分类号： G06F15/00 , G06F21/00 , H04L29/06 , H04L9/00
CPC分类号： H04L63/0245 , G06F21/566 , G06F21/567 , H04L63/1408 , H04L63/145
摘要： The present invention relates generally to a worm blocking system including a dedicated hardware-based board for performing pattern matching without a change in an existing network environment, which is installed in front of a network to be protected, inspects whether worm-related patterns exist on all packets on communication lines without loss or delay, passes packets through the system or blocks packets according to corresponding security rules and informs an administrator of results in real time, and a worm blocking method. In particular, the present invention relates to a hardware-based system and method for detecting and blocking worm-related packets which is suitable for a gigabit environment.
摘要翻译：本发明一般涉及一种包括专用硬件的板，用于执行模式匹配而不改变现有网络环境，该网络环境安装在要保护的网络前面，检查是否存在蠕虫相关模式通信线路上的所有数据包没有丢失或延迟，通过系统传递数据包或根据相应的安全规则阻止数据包，并实时通知管理员结果，以及一种蠕虫阻塞方法。特别地，本发明涉及一种用于检测和阻止适用于千兆环境的蠕虫相关分组的基于硬件的系统和方法。

36. 发明申请

US20050059240A1 Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same 有权
标题翻译：用于形成半导体器件的布线的方法，用于形成半导体器件的金属层的方法及其执行方法
公开(公告)号：US20050059240A1
公开(公告)日：2005-03-17
申请号：US10857253
申请日：2004-05-28
申请人： Kyung-In Choi , Sang-Bom Kang , Seong-Geon Park , You-Kyoung Lee , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Woo Lee
发明人： Kyung-In Choi , Sang-Bom Kang , Seong-Geon Park , You-Kyoung Lee , Gil-Heyun Choi , Jong-Myeong Lee , Sang-Woo Lee
IPC分类号： H01L21/00 , H01L21/44 , H01L21/84
CPC分类号： H01L21/28556 , C23C16/34 , C23C16/45553 , H01L21/28562 , H01L21/76843 , H01L21/7685 , H01L21/76858 , H01L21/76862 , H01L21/76867 , H01L21/76877
摘要： In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1-C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.
摘要翻译：在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。由化学式Ta（NR1）（NR2R3）3表示的钽胺衍生物，其中R 1，R 2和R 3表示H或C 1 -C 6烷基被引入到绝缘中间层上。一部分钽胺衍生物被化学吸附在绝缘中间层上。在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。将反应气体引入到绝缘中间层上。化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

37. 发明授权

US5319284A Electronic ballast circuit for discharge lamp 失效
标题翻译：放电灯电子镇流器电路
公开(公告)号：US5319284A
公开(公告)日：1994-06-07
申请号：US131310
申请日：1993-10-04
申请人： Sang-Woo Lee
发明人： Sang-Woo Lee
IPC分类号： H05B41/298 , H05B37/02
CPC分类号： H05B41/2988
摘要： An electronic ballast circuit for a discharge lamp, comprising a plurality of transistors connected in series across a DC power line, a driving circuit for alternately turning on/off the transistors and a first LC series resonance circuit connected to an output of the driving circuit, the first LC series resonance circuit having a coil and a plurality of condensers. According to the invention, the electronic ballast circuit comprises a damping circuit connected across the coil for absorbing an instantaneously excessive preheating current or a high voltage pulse. The electronic ballast circuit also comprises a plurality of impulse voltage absorbing devices connected at their one sides to an output side of the coil and at their other sides to a high frequency zero potential point of the DC power line for absorbing a contact high voltage pulse generated across the discharge lamp. The electronic ballast circuit further comprises a second LC series resonance circuit connected across the discharge lamp for enhancing a crest factor of a current flowing through the discharge lamp. Therefore, filaments of the discharge lamp are not subjected to a damage resulting from a high crest factor current or a high voltage pulse. This results in an increase in the life of the discharge lamp.
摘要翻译：一种用于放电灯的电子镇流器电路，包括串联连接在直流电源线上的多个晶体管，用于交替地导通/关闭晶体管的驱动电路和连接到驱动电路的输出的第一LC串联谐振电路，第一LC串联谐振电路具有线圈和多个电容器。根据本发明，电子镇流器电路包括连接在线圈两端的阻尼电路，用于吸收瞬时过大的预热电流或高电压脉冲。电子镇流器电路还包括多个脉冲电压吸收装置，它们在其一侧连接到线圈的输出侧，并且在其另一侧连接到DC电力线的高频零电位点，用于吸收产生的接触高电压脉冲穿过放电灯。电子镇流器电路还包括连接在放电灯两端的第二LC串联谐振电路，用于增强流过放电灯的电流的峰值因数。因此，放电灯的灯丝不会受到高波峰因数电流或高压脉冲的损害。这导致放电灯的寿命增加。

38. 发明授权

US5208515A Protection circuit for stabilizer for discharge apparatus 失效
标题翻译：放电装置稳定器保护电路
公开(公告)号：US5208515A
公开(公告)日：1993-05-04
申请号：US805485
申请日：1991-12-11
申请人： Sang-Woo Lee
发明人： Sang-Woo Lee
IPC分类号： H05B41/292
CPC分类号： H05B41/2925 , Y02B20/208 , Y10S315/07
摘要： A protection circuit compatible with an electronic stabilizer of a discharge apparatus, for preventing damage to circuit elements due to an excessive voltage at the premature ignition of a discharge tube, comprises an intermittent switching circuit coupled to a thyristor for periodically turning on or off the thyristor. In the intermittent switching circuit, a first contact point of a relay switch is coupled to the cathode of the thyristor and a resistor, a condensor and a gate of a transistor are connected in parallel from a second contact point of the relay switch and a relay coil and a channel of said transistor are serially connected from the power source and a base of another transistor is coupled to a third contact point of the relay switch, said other transistor controlling the operation of a transistor which drives the discharge tube.
摘要翻译：一种与放电装置的电子稳定器兼容的保护电路，用于防止由放电管过早点火时的过大电压引起的对电路元件的损坏，包括连接到晶闸管的间歇开关电路，用于周期性地导通或关断晶闸管。在间歇切换电路中，继电器开关的第一接点与晶闸管的阴极耦合，并且电阻器，晶体管的电容器和栅极与继电器开关的第二接点并联连接线圈和所述晶体管的通道从电源串联连接，另一晶体管的基极耦合到继电器开关的第三接触点，所述另一晶体管控制驱动放电管的晶体管的操作。

39. 发明授权

US10840374B2 Semiconductor devices with shaped portions of elevated source/drain regions 有权
公开(公告)号：US10840374B2
公开(公告)日：2020-11-17
申请号：US16026614
申请日：2018-07-03
申请人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
发明人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
IPC分类号： H01L29/78 , H01L29/66 , H01L29/40 , H01L21/285 , H01L21/265 , H01L29/165 , H01L23/485 , H01L27/092 , H01L29/08 , H01L29/16 , H01L29/161
CPC分类号： H01L29/7839 , H01L21/26506 , H01L21/28518 , H01L21/28537 , H01L23/485 , H01L27/092 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/1608 , H01L29/401 , H01L29/665 , H01L29/66636 , H01L29/66643 , H01L29/7848 , H01L2924/0002 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

40. 发明授权

US10043902B2 Semiconductor devices with shaped portions of elevated source/drain regions 有权
公开(公告)号：US10043902B2
公开(公告)日：2018-08-07
申请号：US14963731
申请日：2015-12-09
申请人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
发明人： Chung-Hwan Shin , Sang-Bom Kang , Dae-Yong Kim , Jeong-Ik Kim , Chul-Sung Kim , Je-Hyung Ryu , Sang-Woo Lee , Hyo-Seok Choi
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66 , H01L29/40 , H01L21/285 , H01L21/265 , H01L29/165 , H01L23/485 , H01L21/768 , H01L27/092 , H01L29/08 , H01L29/16 , H01L29/161
CPC分类号： H01L29/7839 , H01L21/26506 , H01L21/28 , H01L21/28518 , H01L21/28537 , H01L21/76814 , H01L23/485 , H01L27/092 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/401 , H01L29/665 , H01L29/66636 , H01L29/66643 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

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