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31. 发明授权

US07283410B2 Real-time adaptive SRAM array for high SEU immunity 有权
标题翻译：实时自适应SRAM阵列，具有高SEU抗扰度
公开(公告)号：US07283410B2
公开(公告)日：2007-10-16
申请号：US11308215
申请日：2006-03-13
申请人： Louis L. Hsu , Jack A. Mandelman , Robert C. Wong , Chih-Chao Yang
发明人： Louis L. Hsu , Jack A. Mandelman , Robert C. Wong , Chih-Chao Yang
IPC分类号： G11C7/00
CPC分类号： G11C11/4125
摘要： A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.
摘要翻译：一种用于自动调整存储器件（例如SRAM阵列）中的一个或多个电参数的系统和方法。该系统和方法实现SRAM感测子阵列，用于加速收集故障率数据，用于确定单个事件不起作息和主SRAM阵列性能之间的最佳权衡的操作点。将加速失败率数据输入到在电离粒子环境中将初级SRAM存储器阵列的SEU灵敏度设定为预定故障率的算法。为了提供符合最佳性能的SEU的免疫力，实时地维持预定的故障率。

32. 发明授权

US06869846B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
标题翻译：形成具有双介电厚度的电子结构和如此形成的结构
公开(公告)号：US06869846B2
公开(公告)日：2005-03-22
申请号：US10411850
申请日：2003-04-10
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
摘要翻译：一种包括第一装置和第二装置的结构，其中所述第二装置的电介质厚度大于所述第一装置的电介质厚度，以及形成所述结构的方法。

33. 发明授权

US06724029B2 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US06724029B2
公开(公告)日：2004-04-20
申请号：US09683831
申请日：2002-02-21
申请人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

34. 发明授权

US06573585B2 Electrically blowable fuse with reduced cross-sectional area 有权
公开(公告)号：US06573585B2
公开(公告)日：2003-06-03
申请号：US09769453
申请日：2001-01-26
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

35. 发明授权

US06566191B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US06566191B2
公开(公告)日：2003-05-20
申请号：US09731148
申请日：2000-12-05
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

36. 发明授权

US06563736B2 Flash memory structure having double celled elements and method for fabricating the same 有权
公开(公告)号：US06563736B2
公开(公告)日：2003-05-13
申请号：US09860736
申请日：2001-05-18
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , William R. Tonti
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , William R. Tonti
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/0458 , H01L27/115
摘要： A flash memory array having a plurality of bitlines, at least one wordline and a plurality of flash memory flash memory elements, wherein each flash memory element includes two transistors for storing two bits, and wherein each flash memory element is positioned between a pair of adjacent bitlines. A method is also presented for fabricating the flash memory array having the plurality of flash memory elements, wherein each flash memory element is configured for storing two bits.

37. 发明授权

US06541815B1 High-density dual-cell flash memory structure 失效
标题翻译：高密度双单元闪存结构
公开(公告)号：US06541815B1
公开(公告)日：2003-04-01
申请号：US09974968
申请日：2001-10-11
申请人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
发明人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/7885
摘要： A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions. The memory cell structure further includes bitline diffusion regions formed in the Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to the trenches. The wordlines are in contact with a top surface of each control gate region.
摘要翻译：提供了一种2F2闪存单元结构及其制造方法。 2F2闪存单元结构包括其中形成有多个沟槽的含Si衬底。每个沟槽具有延伸到底壁，长度和包括每个段的两个存储单元元件的单独段的侧壁。每个存储单元元件包括（i）具有形成在每个沟槽侧壁的一部分上的L形栅极的浮栅区域; （ii）重叠在每个沟槽的底壁处的L形门的一侧并沿多个沟槽的整个长度延伸的程序线; 和（iii）覆盖浮栅区域的控制栅极区域。控制栅极区域包括形成在沟槽的侧壁的与浮动栅极区域耦合的部分上的栅极。所述存储单元结构还包括形成在所述含Si半导体衬底中的位线邻接每个沟槽段的位线扩散区; 和与沟槽正交的字线。字线与每个控制栅极区域的顶表面接触。

38. 发明授权

US06274467B1 Dual work function gate conductors with self-aligned insulating cap 失效
标题翻译：具有自对准绝缘帽的双功能栅极导体
公开(公告)号：US06274467B1
公开(公告)日：2001-08-14
申请号：US09327080
申请日：1999-06-04
申请人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2122
CPC分类号： H01L21/28035 , H01L21/28052 , H01L21/32155 , H01L21/823842
摘要： A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack includes a gate insulating layer formed on the substrate and a layer of polysilicon on top of the gate insulating layer. The polysilicon layer may be doped n-type remain intrinsic. A barrier layer is formed on top of the polysilicon layer and a dopant source layer is formed on top of the barrier layer. The barrier layer contains a p-type dopant. The gate stack is enclosed by an insulating cap so that a diffusion contact can be formed borderless to the gate. Activation of the dopant source layer to dope a polysilicon layer can be delayed until a desired time.
摘要翻译：提供一种具有自对准绝缘帽的双功能栅极导体及其形成方法。在衬底中形成两个扩散区域，并且在扩散区域之间的衬底上形成栅叠层。栅极堆叠包括形成在衬底上的栅极绝缘层和位于栅极绝缘层顶部的多晶硅层。多晶硅层可以掺杂n型保持固有。在多晶硅层的顶部形成阻挡层，并且在阻挡层的顶部上形成掺杂剂源层。阻挡层含有p型掺杂剂。栅极堆叠被绝缘盖封闭，使得扩散接触可以形成与栅极无边界。激发掺杂剂源层以掺杂多晶硅层可以被延迟到期望的时间。

39. 发明授权

US06255157B1 Method for forming a ferroelectric capacitor under the bit line 失效
标题翻译：在位线下形成铁电电容器的方法
公开(公告)号：US06255157B1
公开(公告)日：2001-07-03
申请号：US09238853
申请日：1999-01-27
申请人： Louis L. Hsu , David E. Kotecki , Jack A. Mandelman
发明人： Louis L. Hsu , David E. Kotecki , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L27/10855 , H01L27/10888
摘要： A structure and method for forming an integrated circuit structure including forming at least one transistor structure, forming at least one ferroelectric capacitor above the transistor structure, annealing the ferroelectric capacitor, and forming at least one conductive contact between the transistor structure and the ferroelectric capacitor.
摘要翻译：一种用于形成集成电路结构的结构和方法，包括形成至少一个晶体管结构，在所述晶体管结构上方形成至少一个铁电电容器，退火所述铁电电容器，以及在所述晶体管结构和所述铁电电容器之间形成至少一个导电接触。

40. 发明授权

US06245613B1 Field effect transistor having a floating gate 失效
标题翻译：具有浮动栅极的场效应晶体管
公开(公告)号：US06245613B1
公开(公告)日：2001-06-12
申请号：US09556698
申请日：2000-04-24
申请人： Louis L. Hsu , Jack A. Mandelman , Chih-Chun Hu
发明人： Louis L. Hsu , Jack A. Mandelman , Chih-Chun Hu
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/11543
摘要： A field effect transistor which comprises a semiconductor substrate having a source region and a drain region separated by a channel region; a conductive floating gate formed over a first portion of the channel region adjacent to the doped source region and recessed into the semiconductor substrate; and being separated from the first portion of the channel region by a first insulation layer; and a conductive control gate formed substantially over but electrically isolated from the floating gate and formed over the entire channel region; along with a method for fabricating such is provided.
摘要翻译：一种场效应晶体管，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 导电浮置栅极，形成在与掺杂源极区域相邻并且凹入半导体衬底的沟道区域的第一部分上; 并且通过第一绝缘层与沟道区的第一部分分离; 以及导电控制栅极，其形成在所述浮栅上基本上但电隔离并形成在整个沟道区上; 以及其制造方法。

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