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31. 发明申请

US20050174125A1 Multiple voltage level detection circuit 失效
标题翻译：多电压电平检测电路
公开(公告)号：US20050174125A1
公开(公告)日：2005-08-11
申请号：US10776778
申请日：2004-02-11
申请人： Dipankar Bhattacharya , John Kriz , Joseph Simko
发明人： Dipankar Bhattacharya , John Kriz , Joseph Simko
IPC分类号： G01R19/165 , G01R31/08
CPC分类号： G01R19/16595 , G01R19/16519
摘要： A circuit configurable for indicating a voltage level of an input signal applied to the circuit includes at least one transistor having a first terminal connected to a first voltage supply, a second terminal configured for receiving the input signal, and a third terminal operatively coupled to an output of the circuit. The circuit further includes a passive load connected between the third terminal of the transistor and a second voltage supply. The circuit is configured to generate an output signal at the output of the circuit. The output signal being at a first value indicates that the input signal is substantially at a first voltage level, and the output signal being at a second value indicates that the input signal is substantially at a second voltage level.
摘要翻译：可配置为指示施加到电路的输入信号的电压电平的电路包括至少一个晶体管，其具有连接到第一电压源的第一端子，被配置为接收输入信号的第二端子，以及可操作地耦合到输出电路。电路还包括连接在晶体管的第三端子和第二电压源之间的无源负载。电路被配置为在电路的输出处产生输出信号。输出信号处于第一值表示输入信号基本上处于第一电压电平，并且输出信号处于第二值表示输入信号基本上处于第二电压电平。

32. 发明申请

US20070176635A1 Voltage level translator circuit with wide supply voltage range 有权
标题翻译：具有宽电源电压范围的电压电平转换电路
公开(公告)号：US20070176635A1
公开(公告)日：2007-08-02
申请号：US11342175
申请日：2006-01-27
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , H03K3/356104
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.
摘要翻译：用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，该输入级包括至少一个具有第一阈值电压相关联。电压电平转换器电路还包括锁存电路，其操作以存储表示输入信号的逻辑状态的信号，所述锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，所述第二阈值电压大于第一阈值电压。电压钳位电路连接在输入级和锁存电路之间。电压钳位电路用于限制输入级两端的电压，输入级两端的电压幅度作为第一和第二电压源之间的电压差的函数被控制。

33. 发明申请

US20060170462A1 RELIABILITY COMPARATOR WITH HYSTERESIS 有权
标题翻译：可靠性比较器与HYSTERESIS
公开(公告)号：US20060170462A1
公开(公告)日：2006-08-03
申请号：US11047388
申请日：2005-01-31
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris , William Wilson
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris , William Wilson
IPC分类号： H03K5/22
CPC分类号： H03K3/02337 , H03K3/3565
摘要： A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.
摘要翻译：比较器电路包括连接到提供第一电压的第一源的参考发生器。参考发生器用于产生参考信号并且包括响应于第一控制信号选择性地以至少第一模式或第二模式操作的控制电路，其中在第一模式中不产生参考信号，并且在第二模式，参考发生器用于产生参考信号。比较器电路还包括连接到提供第二电压的第二源的比较器，第二电压小于第一电压。比较器用于接收参考信号和输入信号，并且产生作为输入信号和参考信号之间的比较的函数的输出信号。比较器电路中包括滞后电路，用于根据比较器的输出信号选择性地控制比较器相对于输入信号的切换阈值。比较器电路包括电压钳位器，用于将施加到控制电路，比较器和/或滞后电路中的一个或多个器件的电压限制为小于第二电压。

34. 发明申请

US20060145749A1 Bias circuit having reduced power-up delay 审中-公开
标题翻译：偏置电路具有降低的上电延迟
公开(公告)号：US20060145749A1
公开(公告)日：2006-07-06
申请号：US11026426
申请日：2004-12-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Joseph Simko
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： A bias circuit includes a reference generator for generating a bias signal at an output of the reference generator. The reference generator is selectively operable a first mode or a second mode in response to a first control signal applied to the reference generator, wherein in the first mode of operation, the reference generator is disabled, and in the second mode of operation, the reference generator is operative to generate the bias signal. The bias circuit further includes a shunt circuit connected to the reference generator. The shunt circuit is configured to provide a source of current to assist in charging the output of the reference generator to a quiescent operating level during the second mode of operation. The shunt circuit, in response to a second control signal applied thereto, is operable for a selected period time after the reference generator transitions from the first mode of operation to the second mode of operation.
摘要翻译：偏置电路包括用于在参考发生器的输出处产生偏置信号的参考发生器。参考发生器响应于施加到参考发生器的第一控制信号而选择性地操作第一模式或第二模式，其中在第一操作模式中，参考发生器被禁用，并且在第二操作模式中，发生器用于产生偏置信号。偏置电路还包括连接到参考发生器的分流电路。分流电路被配置为提供电流源以帮助在第二操作模式期间将参考发生器的输出充电到静止工作电平。分流电路响应于施加到其上的第二控制信号可在参考发生器从第一操作模式转换到第二操作模式之后的所选时段内操作。

35. 发明申请

US20060103427A1 Overvoltage tolerant input buffer 有权
公开(公告)号：US20060103427A1
公开(公告)日：2006-05-18
申请号：US10988103
申请日：2004-11-12
申请人： Dipankar Bhattacharya , John Kriz , Bernard Morris
发明人： Dipankar Bhattacharya , John Kriz , Bernard Morris
IPC分类号： H03K19/094
CPC分类号： H03K19/00315
摘要： When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied. Another embodiment has two N-channel devices (M12, M13) coupled in series with each other and one of the N-channel devices (M13) being configured in a “turned off” position, by coupling the source and gate terminals to a ground voltage (VSS) and providing the supply voltage (VDD) at the gate terminal of another N-channel device (M12), whereby the device M12 protects the device M13 from overvoltage.

36. 发明申请

US20050134364A1 Reference compensation circuit 有权
标题翻译：参考补偿电路
公开(公告)号：US20050134364A1
公开(公告)日：2005-06-23
申请号：US10744801
申请日：2003-12-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Jeffrey Nagy , Stefan Siegel
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/245 , G05F3/247
摘要： A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.
摘要翻译：补偿电路包括参考电路，该参考电路包括参考NMOS器件和参考PMOS器件。参考电路可操作以产生第一参考信号和第二参考信号，第一参考信号是参考NMOS器件的处理特性，电压特性和温度特性中的至少一个的函数，第二参考信号信号是参考PMOS器件的工艺特性，电压特性和温度特性中的至少一个的函数。补偿电路还包括连接到参考电路的控制电路。控制电路可操作以接收第一和第二参考信号并产生一个或多个输出信号，用于补偿至少一个NMOS器件的工艺特性，电压特性和温度特性中的至少一个的变化，并且在响应于第一和第二参考信号，要补偿的电路中的至少一个PMOS器件可连接到控制电路。

37. 发明授权

US08362803B2 Mode latching buffer circuit 有权
标题翻译：模式锁存缓冲电路
公开(公告)号：US08362803B2
公开(公告)日：2013-01-29
申请号：US13031176
申请日：2011-02-18
申请人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
发明人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K3/356182
摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
摘要翻译：电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及电压钳耦合在输入级和第一锁存电路之间。电压钳可用于将输入级两端的最大电压设定到规定的电平。电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。第二锁存电路以反馈配置连接到第一输出端。第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

38. 发明申请

US20120212256A1 Mode Latching Buffer Circuit 有权
标题翻译：模式锁存缓冲电路
公开(公告)号：US20120212256A1
公开(公告)日：2012-08-23
申请号：US13031176
申请日：2011-02-18
申请人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
发明人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
IPC分类号： H03K19/0175 , H03K5/08
CPC分类号： H03K19/018521 , H03K3/356182
摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
摘要翻译：电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及电压钳耦合在输入级和第一锁存电路之间。电压钳可用于将输入级两端的最大电压设定到规定的电平。电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。第二锁存电路以反馈配置连接到第一输出端。第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

39. 发明申请

US20110187431A1 Voltage Level Translator Circuit 有权
标题翻译：电压电平转换器电路
公开(公告)号：US20110187431A1
公开(公告)日：2011-08-04
申请号：US12598352
申请日：2008-12-29
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356113 , H03K3/0375
摘要： A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).
摘要翻译：电压转换器电路（320）包括适于接收参考第一电压源（VDD核心）的输入信号的输入级（322），适于连接到第二电压源（VDD33）的锁存器（326）至少临时存储输入信号的逻辑状态，以及耦合在输入级（322）和锁存器（326）之间的电压钳位（324）。电压钳（322）用于将锁存器（326）两端的最大电压设定为第一规定电平，并将输入级两端的最大电压设定为第二规定电平。电压转换器电路（320）在闩锁（326）和电压钳（324）之间的连接处产生第一输出信号（II）。电压转换器电路在电压钳位器（324）和输入级（322）之间的接点处产生第二输出信号（15）。

40. 发明授权

US07642807B2 Multiple-mode compensated buffer circuit 有权
标题翻译：多模式补偿缓冲电路
公开(公告)号：US07642807B2
公开(公告)日：2010-01-05
申请号：US11768496
申请日：2007-06-26
申请人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K17/16
CPC分类号： H03K19/00376
摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
摘要翻译：以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。输出块的各输出端连接在一起形成缓冲电路的输出。输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等效于第一模式中的二进制码字的算术移位。

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