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31. 发明授权

US06847568B2 Sense amplifier configuration for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的感测放大器配置
公开(公告)号：US06847568B2
公开(公告)日：2005-01-25
申请号：US10662634
申请日：2003-09-15
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C11/15 , G11C7/06 , G11C7/00
CPC分类号： G11C7/067 , G11C7/062 , G11C2207/063
摘要： A memory sense amplifier for a semiconductor memory device is provided with a compensation current source device that generates a compensation current and feeds it to an interconnected bit line. The compensation current is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device on the selected and interlinked bit line device that is substantially constant over time.
摘要翻译：用于半导体存储器件的存储读出放大器设置有产生补偿电流并将其馈送到互连位线的补偿电流源器件。以这样的方式选择补偿电流，即在读出期间，可以与所选择的和互连的位线装置上的补偿电压源装置协同生成和/或维持电位梯度，所述补偿电压源装置随时间基本上是恒定的。

32. 发明授权

US06778431B2 Architecture for high-speed magnetic memories 有权
标题翻译：高速磁记忆架构
公开(公告)号：US06778431B2
公开(公告)日：2004-08-17
申请号：US10318709
申请日：2002-12-13
申请人： Dietmar Gogl , William Robert Reohr , Roy Edwin Scheuerlein
发明人： Dietmar Gogl , William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C700
CPC分类号： G11C11/1693 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.
摘要翻译：磁存储器电路包括多个存储器单元和耦合到存储器单元的多个位线，用于选择性地访问一个或多个存储器单元。存储器电路包括至少一个位线编程电路，可配置为用于产生用于写入至少一个存储器单元的逻辑状态的编程电流的电流源和/或用于返回编程电流的电流吸收器，以及第一组开关。至少在存储器单元的读取操作期间禁用第一组开关，并且在存储器单元的写入操作期间选择性地使能第一组开关的至少一部分。第一组开关中的每个开关被配置为响应于第一控制信号选择性地将至少一个位线编程电路耦合到对应的位线。存储器电路还包括至少一个读出放大器和第二组开关。至少在存储器单元的写入操作期间禁用第二组开关，并且在存储器单元的读取操作期间，第二组开关的至少一部分被选择性地使能。第二组开关中的每个开关被配置为响应于第二控制信号选择性地将至少一个读出放大器耦合到对应的一个位线。

33. 发明授权

US06639829B2 Configuration and method for the low-loss writing of an MRAM 有权
公开(公告)号：US06639829B2
公开(公告)日：2003-10-28
申请号：US09922471
申请日：2001-08-03
申请人： Dietmar Gogl , Helmut Kandolf , Stefan Lammers
发明人： Dietmar Gogl , Helmut Kandolf , Stefan Lammers
IPC分类号： G11C1100
CPC分类号： G11C5/063 , G11C11/15 , G11C11/16
摘要： A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2

34. 发明授权

US07903454B2 Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit 有权
标题翻译：集成电路，存储单元阵列，存储器模块和操作集成电路的方法
公开(公告)号：US07903454B2
公开(公告)日：2011-03-08
申请号：US12114466
申请日：2008-05-02
申请人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
发明人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
摘要翻译：根据本发明的一个实施例，集成电路包括多个热可选择存储单元，每个存储单元连接到导电线，该导线具有用于施加加热电流的第一部分和用于施加加热电流的第二部分编程电流。集成电路被配置为使得加热电流和编程电流可以彼此独立地分别路由到导线的第一和第二部分。

35. 发明授权

US07411815B2 Memory write circuit 有权
标题翻译：存储器写入电路
公开(公告)号：US07411815B2
公开(公告)日：2008-08-12
申请号：US11273248
申请日：2005-11-14
申请人： Dietmar Gogl
发明人： Dietmar Gogl
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C7/12 , G11C11/16
摘要： A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss and noise problems is described. Positive and negative current sources are provided to supply the bi-directional current that is used to write to a memory cell. These current sources may be selectively connected to bit lines that are electrically connected to the memory cells. Applying a positive current, from the positive current source, through a memory cell writes a “1”, and applying a negative current, from the negative current source, through a memory cell writes a “0”. Use of both a positive and a negative current source enables writing to the memory cells without relying on a switched ground connection to provide bi-directional current. This permits a ground connection of each memory cell to be connected to a fixed ground. An example in which this design is used with a spin injection magneto-resistive random access memory (MRAM) device is shown.
摘要翻译：描述了一种使用双向写入电流并避免用于存储器单元的开关接地连接的存储器阵列的设计，从而减少信号损耗和噪声问题。提供正和负电流源以提供用于写入存储单元的双向电流。这些电流源可以选择性地连接到电连接到存储器单元的位线。从正电流源施加正电流通过存储单元写入“1”，并从负电流源施加负电流通过存储单元写入“0”。使用正电流源和负电流源都可以对存储单元进行写操作，而无需依靠开关式接地连接来提供双向电流。这允许每个存储单元的接地连接到固定地。示出了这种设计与自旋注入磁阻随机存取存储器（MRAM）装置一起使用的示例。

36. 发明申请

US20070189059A1 Memory device and method for reading data 有权
标题翻译：用于读取数据的存储器件和方法
公开(公告)号：US20070189059A1
公开(公告)日：2007-08-16
申请号：US11354281
申请日：2006-02-14
申请人： Dietmar Gogl
发明人： Dietmar Gogl
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C13/04 , G11C2013/0042 , G11C2213/79
摘要： The present invention relates to a memory with memory cells, wherein a memory cell comprises a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches comprise control inputs that are connected with word lines for controlling the switching states, wherein the word lines are connected with a word line driver that supplies selected word lines with a voltage, wherein the bit lines are connected with second switches, wherein the first bit lines are connectable by respective second switches with a first voltage level and the second bit lines are connectable by respective second switches with a second voltage level, wherein a first and a second bit line are connectable as a bit line pair with a sense amplifier, wherein the sense amplifier amplifies a voltage difference between the first and the second bit line of the bit line pair, wherein the resistive element is able to change the resistance depending on an electrical voltage that is applied across the resistive element, and wherein the second voltage level is between the plate voltage level and the first voltage level.
摘要翻译：本发明涉及具有存储单元的存储器，其中存储单元包括电阻元件和开关，其中存储器单元与公共板线和各自的位线连接，其中公共板线提供板电压，其中所述开关包括与用于控制所述开关状态的字线连接的控制输入，其中所述字线与提供所选字线的字线驱动器连接，其中所述位线与第二开关连接，其中，第一位线可由具有第一电压电平的相应的第二开关连接，并且第二位线可由具有第二电压电平的各个第二开关连接，其中第一位线和第二位线可与读出放大器作为位线对连接，其中所述读出放大器放大位线对的第一和第二位线之间的电压差，其中，静态元件能够根据施加在电阻元件上的电压来改变电阻，并且其中第二电压电平在板电压电平和第一电压电平之间。

37. 发明申请

US20070109840A1 Memory write circuit 有权
标题翻译：存储器写入电路
公开(公告)号：US20070109840A1
公开(公告)日：2007-05-17
申请号：US11273248
申请日：2005-11-14
申请人： Dietmar Gogl
发明人： Dietmar Gogl
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C7/12 , G11C11/16
摘要： A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss and noise problems is described. Positive and negative current sources are provided to supply the bi-directional current that is used to write to a memory cell. These current sources may be selectively connected to bit lines that are electrically connected to the memory cells. Applying a positive current, from the positive current source, through a memory cell writes a “1”, and applying a negative current, from the negative current source, through a memory cell writes a “0”. Use of both a positive and a negative current source enables writing to the memory cells without relying on a switched ground connection to provide bi-directional current. This permits a ground connection of each memory cell to be connected to a fixed ground. An example in which this design is used with a spin injection magneto-resistive random access memory (MRAM) device is shown.
摘要翻译：描述了一种使用双向写入电流并避免用于存储器单元的开关接地连接的存储器阵列的设计，从而减少信号损耗和噪声问题。提供正和负电流源以提供用于写入存储单元的双向电流。这些电流源可以选择性地连接到电连接到存储器单元的位线。从正电流源施加正电流通过存储单元写入“1”，并从负电流源施加负电流通过存储单元写入“0”。使用正电流源和负电流源都可以对存储单元进行写操作，而无需依靠开关式接地连接来提供双向电流。这允许每个存储单元的接地连接到固定地。示出了这种设计与自旋注入磁阻随机存取存储器（MRAM）装置一起使用的示例。

38. 发明授权

US07161861B2 Sense amplifier bitline boost circuit 有权
标题翻译：感应放大器位线升压电路
公开(公告)号：US07161861B2
公开(公告)日：2007-01-09
申请号：US10988787
申请日：2004-11-15
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02 , G11C7/00
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/16 , G11C2207/063
摘要： A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
摘要翻译：包括钳位装置和电流镜的电流检测放大器被配置为使用位线升压电路感测MTJ存储器单元的电阻，以缩短寄生电路电容的充电时间。位线升压电路包括耦合到参考电压的源极跟随器和耦合到另一个电压源的开关。在感测存储单元的电阻的初始时段期间，该开关能够导通。位线升压电路中的源极跟随器被配置为将输入信号的电压钳位在与钳位装置基本相同的电平上，并提供额外的电流以缩短对寄生电容充电的周期。所得到的电流检测放大器可用于实现具有快速可靠的读取时间和低制造成本的存储器件。

39. 发明申请

US20060289970A1 Magnetic shielding of MRAM chips 审中-公开
标题翻译： MRAM芯片的磁屏蔽
公开(公告)号：US20060289970A1
公开(公告)日：2006-12-28
申请号：US11168203
申请日：2005-06-28
申请人： Dietmar Gogl , Daniel Braun
发明人： Dietmar Gogl , Daniel Braun
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , G11C11/15 , H01L23/29 , H01L2224/16 , H01L2924/3025
摘要： An apparatus comprising a magnetically shielded MRAM chip and a method of manufacturing the same. The apparatus includes an MRAM module and a protective cover. The MRAM module includes a circuit board and a memory chip attached to the circuit board, the memory chip containing magnetoresistive random access memory (MRAM) cells. The protective cover includes a magnetic shielding material and at least partially encloses the memory chip. In another embodiment, the protective cover shields the memory chip without shielding at least a portion of the circuit board.
摘要翻译：一种包括磁屏蔽MRAM芯片的装置及其制造方法。该装置包括MRAM模块和保护盖。 MRAM模块包括电路板和连接到电路板的存储器芯片，该存储器芯片包含磁阻随机存取存储器（MRAM）单元。保护盖包括磁屏蔽材料并且至少部分地包围存储芯片。在另一个实施例中，保护盖屏蔽存储芯片，而不屏蔽电路板的至少一部分。

40. 发明申请

US20060114713A1 MRAM with coil for creating offset field 有权
标题翻译：带有线圈的MRAM用于创建偏移场
公开(公告)号：US20060114713A1
公开(公告)日：2006-06-01
申请号：US10998808
申请日：2004-11-30
申请人： Daniel Braun , Dietmar Gogl
发明人： Daniel Braun , Dietmar Gogl
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , G11C11/16
摘要： An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a magnetic offset field. Further, a method of writing to an MRAM chip includes bringing the memory cells into an active state exhibiting a reduced switching field before writing thereto and bringing the memory cells into a passive state exhibiting enlarged switching field after writing thereto.
摘要翻译： MRAM存储器芯片包括多个磁阻存储单元，每个磁阻存储单元包括具有第一（固定）和第二（自由）磁区的磁性隧道结，其中第二磁区包括反铁磁耦合的至少两个铁磁层，其中线圈围绕用于产生磁偏移场的存储芯片。此外，写入MRAM芯片的方法包括在写入之前使存储单元进入呈现减小的开关场的有效状态，并且在写入之后使存储单元成为展现放大开关场的被动状态。

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