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31. 发明授权

US5830773A Method for forming semiconductor field region dielectrics having globally planarized upper surfaces 失效
标题翻译：用于形成具有全局平坦化的上表面的半导体场区电介质的方法
公开(公告)号：US5830773A
公开(公告)日：1998-11-03
申请号：US634757
申请日：1996-04-17
申请人： William S. Brennan , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Mark W. Michael
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/768 , H01L21/31
CPC分类号： H01L21/76819 , H01L21/31055 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer. After etch removal predominantly at the higher elevational regions, the remaining fill dielectric upper surface is removed to a level commensurate with the upper surface of silicon mesas thereby producing separate field dielectrics interposed between silicon mesas. The field dielectrics, regardless of their lateral area, each have a substantially planar upper surface at or slightly below the adjoining silicon mesas. By producing planar field dielectric upper surfaces, various problems of non-planarity are removed from the thin films which are thereafter formed on the field dielectrics or between the field dielectrics and silicon mesas.
摘要翻译：提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。隔离过程导致间隔开的多个场电介质，其具有彼此基本上共面的上表面和相邻的硅台面上表面。因此，隔离过程是与浅沟槽技术一起使用的平坦化工艺，其中将蚀刻增强离子转移到该电介质的上部高度区域的填充电介质中。当经受随后的蚀刻剂时，掺杂剂导致以比较低的高度区域更快的速率除去较高的高度区域。因此，掺杂剂的选择性放置和蚀刻去除预先将填充电介质上表面全局地横跨整个晶片进行预处理。在主要在较高高度区域蚀刻去除之后，将剩余的填充电介质上表面去除到与硅台面的上表面相当的水平，由此产生介于硅台面之间的单独的场电介质。场电介质，无论它们的横向面积如何，每个在相邻的硅台面处或稍低于相邻的硅台面处都具有基本平坦的上表面。通过产生平面场电介质上表面，从形成在场电介质上或场电介质和硅台面之间的薄膜中去除了各种非平面性问题。

32. 发明授权

US5792706A Interlevel dielectric with air gaps to reduce permitivity 失效
标题翻译：具有气隙的层间电介质以降低介电常数
公开(公告)号：US5792706A
公开(公告)日：1998-08-11
申请号：US658457
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： A reduced permittivity interlevel dielectric is provided. The interlevel dielectric is formed between two levels of interconnect. The interlevel dielectric comprises a first dielectric layer formed from a TEOS source deposited on a first level interconnect. The first dielectric contains air gaps at spaced intervals across the first dielectric. A second dielectric, preferably from a silane source is deposited upon said first dielectric. A second interconnect level is then placed on the second dielectric.
摘要翻译：提供了一种降低介电常数的层间电介质。层间电介质形成在两层互连之间。层间电介质包括由沉积在第一层互连上的TEOS源形成的第一介质层。第一电介质以间隔开的间隔跨越第一电介质。第二电介质，优选由硅烷源沉积在所述第一电介质上。然后将第二互连电平放置在第二电介质上。

33. 发明授权

US5767012A Method of forming a recessed interconnect structure 失效
标题翻译：形成凹陷互连结构的方法
公开(公告)号：US5767012A
公开(公告)日：1998-06-16
申请号：US660674
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , H01L21/283
CPC分类号： H01L23/5222 , H01L21/768 , H01L2924/0002
摘要： A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, forming a second dielectric on the conductive material and the first dielectric layer.
摘要翻译：提供一种形成凹陷互连结构的方法。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。形成凹陷互连结构的方法包括在半导体衬底上形成基本共面的第一导体组，在第一导体上沉积第一电介质层，在第一电介质层中形成沟槽，在沟槽中沉积导电材料，对导电材料进行平面化，导电材料的上表面与第一电介质的上表面基本共面，蚀刻导电材料，直到导电材料的上表面位于第一电介质的上表面以下，形成第二电介质在导电材料和第一介电层上。

34. 发明授权

US5766803A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
公开(公告)号：US5766803A
公开(公告)日：1998-06-16
申请号：US659165
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , G03F9/00
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

35. 发明授权

US5733798A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
公开(公告)号：US5733798A
公开(公告)日：1998-03-31
申请号：US655247
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

36. 发明授权

US5717242A Integrated circuit having local interconnect for reduing signal cross coupled noise 失效
公开(公告)号：US5717242A
公开(公告)日：1998-02-10
申请号：US633473
申请日：1996-04-17
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L23/5222 , H01L21/76895 , H01L23/5286 , H01L27/11 , H01L2924/0002
摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

37. 发明授权

US06376330B1 Dielectric having an air gap formed between closely spaced interconnect lines 失效
标题翻译：电介质具有形成在紧密间隔的互连线之间的气隙
公开(公告)号：US06376330B1
公开(公告)日：2002-04-23
申请号：US08655242
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L2176
CPC分类号： H01L21/7682
摘要： A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.
摘要翻译：提供一种电介质材料，其具有在电介质中有目的地形成的气隙。电介质被沉积，并且在相应的互连线之间形成气隙。有意地控制互连线之间的几何形状以实现在电介质CVD期间产生气隙所需的大的纵横比。互连之间存在空隙，以减少线间电容，从而减少与紧密间隔的互连相关的传播延迟。

38. 发明授权

US6127719A Subfield conductive layer and method of manufacture 失效
标题翻译：子场导电层及其制造方法
公开(公告)号：US6127719A
公开(公告)日：2000-10-03
申请号：US038464
申请日：1998-03-11
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/74 , H01L29/00 , H01L31/119
CPC分类号： H01L21/74
摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
摘要翻译：提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。在形成场电介质之后，将子场导电层置于硅衬底内。导电层表示驻留在隔离器件之间的掩埋互连。然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

39. 发明授权

US5968843A Method of planarizing a semiconductor topography using multiple polish pads 失效
标题翻译：使用多个抛光垫平面化半导体形貌的方法
公开(公告)号：US5968843A
公开(公告)日：1999-10-19
申请号：US768278
申请日：1996-12-18
申请人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/302
CPC分类号： H01L21/31053
摘要： An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.
摘要翻译：一种用于平坦化层间电介质的改进方法，包括两个化学机械抛光步骤。在形成包含一对形貌峰之间的形貌谷的层间电介质之后，使用具有第一刚性的第一抛光垫在第一抛光步骤中以第一力进行化学机械抛光的电介质以使尖锐的电介质拐角或边缘存在于峰谷之间的过渡处。在第一抛光步骤使边缘变圆之后，用第二刚性的第二抛光垫进行第二抛光步骤。第二抛光垫比第一抛光垫更刚性，第二抛光垫大于第一抛光垫。第二抛光步骤使用高粘度浆料来减少靠近电介质谷的区域中的浆料周转，从而减少了谷中的化学蚀刻并提高了平坦化效率。

40. 发明授权

US5783864A Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect 失效
公开(公告)号：US5783864A
公开(公告)日：1998-07-21
申请号：US655248
申请日：1996-06-05
申请人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/522 , H01L29/41
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.

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