专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20100283121A1 ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS 有权
标题翻译：具有分层尺寸的电熔丝和电阻
公开(公告)号：US20100283121A1
公开(公告)日：2010-11-11
申请号：US12765275
申请日：2010-04-22
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

32. 发明授权

US07394110B2 Planar vertical resistor and bond pad resistor 有权
标题翻译：平面垂直电阻和接合焊盘电阻
公开(公告)号：US07394110B2
公开(公告)日：2008-07-01
申请号：US11307404
申请日：2006-02-06
申请人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
发明人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L23/62
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译：公开了避免半导体器件小型化的问题的电阻器及相关方法。在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。这两个实施方案可以单独使用或一起使用。还公开了用于产生电阻器的相关方法。

33. 发明授权

US06649531B2 Process for forming a damascene structure 有权
标题翻译：形成镶嵌结构的方法
公开(公告)号：US06649531B2
公开(公告)日：2003-11-18
申请号：US09994340
申请日：2001-11-26
申请人： William J. Cote , Timothy J. Dalton , Prakash Chimanlal Dev , Daniel C. Edelstein , Scott D. Halle , Gill Yong Lee , Arpan P. Mahorowala
发明人： William J. Cote , Timothy J. Dalton , Prakash Chimanlal Dev , Daniel C. Edelstein , Scott D. Halle , Gill Yong Lee , Arpan P. Mahorowala
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/31633
摘要： A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.
摘要翻译：用于形成镶嵌结构的方法包括将包括第一介电层和第二介电层的双层沉积到基板上，其中第一层具有高于第二层的介电常数，并且其中第二层选自低k 包含Si，C，O和H的介电材料。使用高选择性各向异性反应离子蚀刻，将多步镶嵌结构图案化成电介质双层。使用等离子体灰化处理从基板去除光致抗蚀剂，聚合物和后蚀刻残留物，而不损坏下面的介电层。

34. 发明授权

US09245794B2 Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application 有权
标题翻译：通过扩散阻挡层和种子层的反应形成合金衬里，用于互连应用
公开(公告)号：US09245794B2
公开(公告)日：2016-01-26
申请号：US13614492
申请日：2012-09-13
申请人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami
发明人： Chih-Chao Yang , Daniel C. Edelstein , Takeshi Nogami
IPC分类号： H05K1/09 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76846 , H01L21/76844 , H01L21/76858 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.
摘要翻译：提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。

35. 发明授权

US09059251B2 Microelectronic structure including air gap 有权
公开(公告)号：US09059251B2
公开(公告)日：2015-06-16
申请号：US13614524
申请日：2012-09-13
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/768
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

36. 发明授权

US08765602B2 Doping of copper wiring structures in back end of line processing 有权
标题翻译：在线路处理后端掺杂铜线结构
公开(公告)号：US08765602B2
公开(公告)日：2014-07-01
申请号：US13599256
申请日：2012-08-30
申请人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
发明人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
摘要翻译：形成金属互连结构的方法包括在层间电介质（ILD）层内形成铜线; 用铜合金材料直接掺杂铜线的顶面; 并在ILD层和铜合金材料上形成介电层; 其中所述铜合金材料用于所述铜线和所述电介质层之间的粘合界面层。

37. 发明申请

US20140061915A1 PREVENTION OF THRU-SUBSTRATE VIA PISTONING USING HIGHLY DOPED COPPER ALLOY SEED LAYER 审中-公开
标题翻译：通过使用高度掺杂的铜合金层进行活化预防基底
公开(公告)号：US20140061915A1
公开(公告)日：2014-03-06
申请号：US13599295
申请日：2012-08-30
申请人： Christopher N. Collins , Daniel C. Edelstein , Mukta G. Farooq , Troy L. Graves-Abe , Andrew H. Simon , Richard P. Volant
发明人： Christopher N. Collins , Daniel C. Edelstein , Mukta G. Farooq , Troy L. Graves-Abe , Andrew H. Simon , Richard P. Volant
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/76873 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/94 , H01L2224/32145 , H01L2224/8001 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/83203 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06541 , H01L2224/83 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.
摘要翻译：形成集成电路器件的方法包括在限定在衬底中的开口中形成扩散阻挡层; 在所述扩散阻挡层上形成高掺杂的铜合金种子层，所述铜合金种子层具有浓度大于0.5％原子的少数合金成分; 以及在所述铜合金晶种层上形成铜层，以限定所述集成电路器件的布线结构。

38. 发明申请

US20140024146A1 SEMICONDUCTOR STRUCTURE 审中-公开
公开(公告)号：US20140024146A1
公开(公告)日：2014-01-23
申请号：US13565848
申请日：2012-08-03
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L21/768 , H01L21/50 , H01L21/66
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

39. 发明授权

US08564132B2 Tungsten metallization: structure and fabrication of same 失效
标题翻译：钨金属化：其结构和制造相同
公开(公告)号：US08564132B2
公开(公告)日：2013-10-22
申请号：US13211722
申请日：2011-08-17
申请人： Chih-Chao Yang , Daniel C. Edelstein
发明人： Chih-Chao Yang , Daniel C. Edelstein
IPC分类号： H01L23/482
CPC分类号： H01L21/76838 , H01L21/76814 , H01L21/76831 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76885 , H01L21/76895
摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.
摘要翻译：提供局部互连结构，其中形成在中间线（MOL）电介质材料内的钨区域，即钨柱，在多重互连图案化工艺期间不被损坏和/或污染。这在本公开内容中通过在顶部表面内形成自对准的氮化钨钝化层，并且在钨区域的上侧壁部分之上延伸到包括形成在其中的第一互连图案的MOL介电材料之上。在自对准氮化钨钝化层的形成过程中，还会在MOL介电材料的暴露表面内形成富含氮的电介质表面。然后形成与第一互连图案相邻但不连接的第二布线图案。由于在钨区域上存在自对准的氮化钨钝化层，不会发生钨区域的破坏和/或污染。

40. 发明授权

US08497580B2 Noble metal cap for interconnect structures 有权
标题翻译：用于互连结构的贵金属盖
公开(公告)号：US08497580B2
公开(公告)日：2013-07-30
申请号：US13191090
申请日：2011-07-26
申请人： Chih-Chao Yang , Daniel C. Edelstein , Fenton R. McFeely
发明人： Chih-Chao Yang , Daniel C. Edelstein , Fenton R. McFeely
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76826 , H01L21/76849 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.
摘要翻译：提供了包括具有约3.0或更小介电常数的介电材料的互连结构。该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料。电介质材料还具有在形成贵金属盖之前被制成疏水性的表面层。贵金属盖直接位于至少一个导电材料的上表面上。由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物沉积形式在该疏水电介质表面上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式