会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 31. 发明授权
    • IC analog debugging and calibration thereof
    • IC模拟调试和校准
    • US07203613B1
    • 2007-04-10
    • US10830881
    • 2004-04-23
    • Gin S. YeeClaude R. Gauthier
    • Gin S. YeeClaude R. Gauthier
    • G01R31/00
    • G01R19/252G01R31/316G01R31/31705
    • An analog debugging block of an integrated circuit includes a multiplexor, a buffer, and a voltage-controlled oscillator. An analog voltage signal-of-interest is selectively passed through the multiplexor to the buffer. The buffer outputs an analog control voltage dependent on the selected analog voltage signal-of-interest. The analog control voltage serves as an input to the voltage-controlled oscillator and is used to control a frequency of a digital output signal generated from the voltage-controlled oscillator. The digital output signal from the voltage-controlled oscillator is driven off-chip, whereupon a frequency of the digital output signal is determined and compared against a collection of known frequencies that correspond to particular known voltages of the analog voltage signal-of-interest, thereby resulting in a determination of the value of the selected analog voltage signal-of-interest.
    • 集成电路的模拟调试块包括多路复用器,缓冲器和压控振荡器。 选择性地将模拟电压信号信号通过多路复用器传送到缓冲器。 缓冲器输出取决于所选模拟电压信号的模拟控制电压。 模拟控制电压用作压控振荡器的输入,用于控制从压控振荡器产生的数字输出信号的频率。 来自压控振荡器的数字输出信号被驱动离开芯片,由此确定数字输出信号的频率并将其与对应于模拟电压感兴趣信号的特定已知电压的已知频率的集合进行比较, 从而导致所选择的模拟电压信号信号的值的确定。
    • 32. 发明授权
    • Receiver-side adaptive equalization in source-synchronous chip-to-chip communication systems
    • 源同步芯片到芯片通信系统中的接收机侧自适应均衡
    • US07154972B2
    • 2006-12-26
    • US10325542
    • 2002-12-18
    • Aninda K. RoyClaude R. Gauthier
    • Aninda K. RoyClaude R. Gauthier
    • H04B1/10
    • H04L25/14
    • A communication system comprising transmitting circuitry arranged to transmit a data signal and a timing signal; and receiving circuitry arranged to receive the data signal and the timing signal. The receiving circuitry comprises a first finite impulse response filter arranged to generate a filtered timing signal dependent on the timing signal and a at least one mixer signal; a decision feedback circuit arranged to generate the at least one mixer signal dependent on the filtered timing signal and a calibration signal; and a second finite impulse response filter arranged to generate a filtered data signal dependent on the data signal and the at least one mixer signal.
    • 一种通信系统,包括被布置为发送数据信号和定时信号的发送电路; 以及接收电路,被布置成接收数据信号和定时信号。 接收电路包括第一有限脉冲响应滤波器,其布置成根据定时信号和至少一个混频器信号产生经滤波的定时信号; 决定反馈电路,被配置为根据滤波的定时信号和校准信号产生至少一个混频器信号; 以及第二有限脉冲响应滤波器,其布置成根据所述数据信号和所述至少一个混频器信号产生经滤波的数据信号。
    • 34. 发明授权
    • Updating high speed parallel I/O interfaces based on counters
    • 基于计数器更新高速并行I / O接口
    • US07062688B2
    • 2006-06-13
    • US10196384
    • 2002-07-16
    • Claude R. GauthierAninda K. RoyBrian W. AmickDean Liu
    • Claude R. GauthierAninda K. RoyBrian W. AmickDean Liu
    • G01R31/28
    • G06F11/24
    • A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.
    • 用于调整通信系统的技术涉及链路,其中链路包括被布置为发送数据信号的数据线和适于发送时钟信号的时钟线。 该技术使用一个或多个计数器来测试链路上的传输。 根据一个或多个这些计数器,连接到链路的测试电路将已知的测试模式信号与在数据线上发送的锁存的测试模式信号进行比较。 该测试电路包括调整电路,该调整电路被布置成从时钟信号产生可调节的时钟信号,其中可调节时钟信号确定何时锁存发送的测试图形信号。测试电路相对于数据信号的数据信号调整可调节时钟信号的定时 链接。