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    • 40. 发明授权
    • Protective hardmask for producing interconnect structures
    • 用于生产互连结构的保护硬掩模
    • US06720249B1
    • 2004-04-13
    • US09550943
    • 2000-04-17
    • Timothy J. DaltonChristopher V. JahnesJoyce C. LiuSampath Purushothaman
    • Timothy J. DaltonChristopher V. JahnesJoyce C. LiuSampath Purushothaman
    • H01L214763
    • H01L21/76835H01L21/76802H01L21/76811H01L21/76813H01L21/76816H01L21/76829H01L23/5222H01L23/5329H01L2924/0002H01L2924/00
    • The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide BLoK™, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric.
    • 本发明提供一种永久性保护性硬掩模,其保护半导体器件中具有期望的低介电常数的主电介质层的介电性能,不需要介电常数的增加,不期望的电流泄漏增加,以及在表面划伤期间的低的器件产量 后续处理步骤。 保护性硬掩模还包括单层或双层牺牲硬掩模,在制造最终产品的过程中,在低电介质材料中形成诸如通孔开口和/或线之间的互连结构时尤其有用。 牺牲硬掩模层和永久硬掩模层可以从相同的前体在单个步骤中形成,其中改变工艺条件以提供不同介电常数的膜。 最优选地,双镶嵌结构具有三层硬掩模,其在形成层间的互连结构之前分别形成在体低介电常数层间电介质上的碳化硅BLoK TM,PECVD氮化硅和PECVD二氧化硅 电介质。