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31. 发明申请

US20100100713A1 FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES 有权
标题翻译：快速浮动点与用于角膜的SLOWER BACKUP比较
公开(公告)号：US20100100713A1
公开(公告)日：2010-04-22
申请号：US12255968
申请日：2008-10-22
申请人： Maarten J. Boersma , Michael Kroener , Silvia M. Meuller , Jochen Preiss
发明人： Maarten J. Boersma , Michael Kroener , Silvia M. Meuller , Jochen Preiss
IPC分类号： G06F9/302
CPC分类号： G06F9/30021 , G06F9/30025
摘要： A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
摘要翻译：浮点处理器单元通过比较整数格式的两个操作数来执行具有相同或不同精度的两个操作数的浮点比较指令，这显着地加快了浮点比较指令的执行。浮点处理器现在对于几乎大多数操作数情况（例如，所有情况的99％），至少执行两倍快或更快（例如，现有技术中的两个时钟周期而不是五个时钟周期）的浮点比较指令。只有罕见的角落情况需要在其中一个操作数上进行额外的操作，因此需要额外的执行周期，因为整数比较操作将不适用于这些角色。这是由于一个操作数是非正规化表示中的单精度子正规数（即，具有两个表示），另一个操作数处于SP子正常范围，使得整数比较操作将失败。

32. 发明申请

US20100095099A1 SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS IN A REGISTER FILE 有权
标题翻译：用于在寄存器文件中存储第一和第二格式的数字的系统和方法
公开(公告)号：US20100095099A1
公开(公告)日：2010-04-15
申请号：US12250935
申请日：2008-10-14
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F9/302 , G06F9/312 , G06F7/38
CPC分类号： G06F9/30025 , G06F7/57 , G06F9/30014 , G06F9/30105 , G06F9/30112 , G06F9/30192 , G06F2207/3824
摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
摘要翻译：提供了一种用于将数字存储在寄存器文件中的系统和方法。系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

33. 发明申请

US20100063985A1 NORMALIZER SHIFT PREDICTION FOR LOG ESTIMATE INSTRUCTIONS 失效
标题翻译：用于日志估计指令的正则化移位预测
公开(公告)号：US20100063985A1
公开(公告)日：2010-03-11
申请号：US12208439
申请日：2008-09-11
申请人： Maarten J. Boersma , Michael Klein , Jochen Preiss , Son Dao Trong
发明人： Maarten J. Boersma , Michael Klein , Jochen Preiss , Son Dao Trong
IPC分类号： G06F7/00
CPC分类号： G06F7/74
摘要： A floating point processor unit includes a shift amount calculation circuit within a normalizer portion of the floating point unit, wherein the shift amount calculation circuit is utilized to compute the normalizer shift amount for a log estimate instruction that runs as a pipelinable instruction.
摘要翻译：浮点处理器单元包括在浮点单元的归一化部分内的移位量计算电路，其中移位量计算电路用于计算作为可流水线指令运行的对数估计指令的归一化器移位量。

34. 发明申请

US20100023573A1 EFFICIENT FORCING OF CORNER CASES IN A FLOATING POINT ROUNDER 有权
标题翻译：在浮动点圆环中有效地施加拐角
公开(公告)号：US20100023573A1
公开(公告)日：2010-01-28
申请号：US12177346
申请日：2008-07-22
申请人： Maarten J. Boersma , J. Adam Butts , Silvia M. Mueller , Jochen Preiss
发明人： Maarten J. Boersma , J. Adam Butts , Silvia M. Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/49947
摘要： The forcing of the result or output of a rounder portion of a floating point processor occurs only in a fraction non-increment data path within the rounder and not in the fraction increment data path within the rounder. The fraction forcing is active on a corner case such as a disabled overflow exception. A disabled overflow exception may be detected by inspecting the normalized exponent. If a disabled overflow exception is detected, the round mode is selected to execute only in the non-increment data path thereby preventing the fraction increment data path from being selected.
摘要翻译：强制浮点处理器的较圆形部分的结果或输出仅在舍入器内的分数非递增数据路径中发生，而不在舍入器内的分数增量数据路径中。部分强制在角落外部活动，例如禁用的溢出异常。可以通过检查归一化指数来检测到禁用的溢出异常。如果检测到禁用的溢出异常，则选择循环模式仅在非增量数据路径中执行，从而防止分数增量数据路径被选择。

35. 发明授权

US07639046B2 Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit 失效
标题翻译：降低时钟门控同步电路和时钟门控同步电路的功耗的方法
公开(公告)号：US07639046B2
公开(公告)日：2009-12-29
申请号：US11850736
申请日：2007-09-06
申请人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
发明人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
IPC分类号： H03K19/00 , H03K17/16 , H03K19/003 , G06F1/00 , G05F1/10 , G05F3/02
CPC分类号： H03K19/0016
摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.
摘要翻译：一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号通过时钟门控同步电路。

36. 发明申请

US20080276140A1 SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS AND A METHOD FOR SCANNING STORAGE ELEMENTS ON A SEMICONDUCTOR CHIP 有权
标题翻译：具有多重可扫描存储元件的半导体芯片和用于扫描半导体芯片上的存储元件的方法
公开(公告)号：US20080276140A1
公开(公告)日：2008-11-06
申请号：US12042944
申请日：2008-03-05
申请人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
发明人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575
摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.
摘要翻译：分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择。

37. 发明申请

US20080169842A1 DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT 失效
标题翻译：在时钟门控同步电路和时钟门控同步电路中降低功耗的设计结构
公开(公告)号：US20080169842A1
公开(公告)日：2008-07-17
申请号：US11850745
申请日：2007-09-06
申请人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
发明人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.
摘要翻译：一种用于降低时钟门控同步电路内的功耗的设计结构，所述同步电路包括至少两个连续级，其中每个级如果被激活，则逐周期地将数据信号周期传播到后级，所述两个连续级包括至少一个控制寄存器，数据寄存器和本地时钟缓冲器（LCB），其中每个级如果被激活，则将周期内存储的数据信号周期传播到后级的数据寄存器。

38. 发明申请

US20080169841A1 METHOD TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT 失效
标题翻译：降低时钟门控同步电路和时钟门控同步电路中的功耗的方法
公开(公告)号：US20080169841A1
公开(公告)日：2008-07-17
申请号：US11850736
申请日：2007-09-06
申请人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
发明人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.
摘要翻译：一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号通过时钟门控同步电路。

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