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    • 33. 发明申请
    • Verifying authenticity of instant messaging messages
    • 验证即时消息消息的真实性
    • US20080307513A1
    • 2008-12-11
    • US11811306
    • 2007-06-07
    • Stanley ChowJeff SmithChristophe Gustave
    • Stanley ChowJeff SmithChristophe Gustave
    • H04L9/32
    • H04L51/04H04L51/12H04L63/0823H04L63/126
    • A certificate registry system is configured to issue authentication certificates to each one of a plurality of information providers and to maintain a root certificate corresponding to all of the authentication certificates. Each one of the authentication certificates links respective authentication information thereof to identification information of a corresponding one of the information providers. Each one of the authentication certificates includes a respective Instant Messaging (IM) screen name information of the information provider. The authentication certificates of the certificate registry are associated in a manner at least partially dependent upon at least one of a particular type of information that the information providers provide, a particular organization that the information providers are associated with, a particular type profession in which the information providers are engaged and a particular geographical region in which the information providers are located.
    • 证书注册系统被配置为向多个信息提供者中的每个信息提供者发送认证证书,并且维护与所有认证证书相对应的根证书。 每个认证证书将其相应的认证信息链接到相应的一个信息提供者的识别信息。 每个认证证书包括信息提供者的相应即时消息(IM)屏幕名称信息。 证书注册管理机构的认证证书至少部分地取决于信息提供者提供的特定类型的信息,信息提供者所关联的特定组织,特定类型职业中的至少一个,其中 信息提供者参与信息提供者所在的特定地理区域。
    • 34. 发明授权
    • Horseshoe
    • 马蹄铁
    • US06688401B2
    • 2004-02-10
    • US10180474
    • 2002-06-25
    • Jeff Smith
    • Jeff Smith
    • A01L302
    • A01L5/00
    • A horseshoe made from rubber or an elastomeric material has a tread portion with a plurality of interconnected side-by-side hollow cylindrical buttons. The buttons are open at their upper ends and their lower ends are covered by a thin film of the rubber or elastomeric material. The horseshoe is attached to the horse's hoof with an adhesive and sufficient adhesive is applied to the tread portion to fill the buttons with adhesive material and provide a thin layer of the adhesive material between the tread portion and the hoof when the horseshoe is pushed toward the hoof.
    • 由橡胶或弹性体材料制成的马掌具有具有多个互相并排的中空圆柱形按钮的胎面部分。 按钮在其上端开口,并且其下端由橡胶或弹性体材料的薄膜覆盖。 马蹄铁用粘合剂连接到马的蹄上,并且足够的粘合剂被施加到胎面部分以用粘合剂材料填充按钮,并且当马掌被推向所述马掌时,在胎面部分和蹄之间提供薄层的粘合材料 蹄。
    • 36. 发明授权
    • Multi-ported memory architecture using single-ported RAM
    • 使用单端口RAM的多端口存储器架构
    • US06212607B1
    • 2001-04-03
    • US08783923
    • 1997-01-17
    • Michael MillerJohn MickJeff SmithMark BaumannChris Schott
    • Michael MillerJohn MickJeff SmithMark BaumannChris Schott
    • G06F1200
    • G11C7/1075G11C2207/104
    • A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0˜401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0˜405-7, 406-0˜406-7, 407-0˜407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L˜2500-3L, 2500-0R˜2500-3R), interrupt generating circuitry (2514-0L˜2514-3L, 2514-0R˜2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L˜3102L, 3101R˜3102R, 3301L˜3302L, 3301R˜3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
    • 具有用于与左(205)和右(206)电子设备通信的左(203)和右(204)端口的存储设备(201)包括存储体(401-0〜401-7),信号量逻辑(302) ,和端口耦合电路(403,404,405-0〜405-7,406-0〜406-7,407-0〜407-7)。 信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号(313,314),并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口 银行存取授权信号。 内存中还包括邮箱寄存器(2500-0L〜2500-3L,2500-0R〜2500-3R),中断发生电路(2514-0L〜2514-3L,2514-0R〜2514-3R,2900 ,3000,307,308),以及中断状态和原因寄存器(3101L〜3102L,3101R〜3102R,3301L〜3302L,3301R〜3302R)。 左右电子设备使用邮箱寄存器相互发送消息,无需等待。 中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备,并且当消息已被写入其中一个邮箱寄存器时。 中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息,哪些邮箱寄存器包含用于它们的消息。
    • 37. 发明授权
    • Mail-box design for non-blocking communication across ports of a
multi-port device
    • 用于多端口设备端口之间的非阻塞通信的邮箱设计
    • US5751638A
    • 1998-05-12
    • US786401
    • 1997-01-17
    • John MickMichael MillerJeff SmithMark Baumann
    • John MickMichael MillerJeff SmithMark Baumann
    • G06F5/10G06F9/46G11C8/16G11C13/00
    • G06F5/10G06F9/52G11C8/16
    • A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
    • 具有用于与左(205)和右(206)电子设备进行通信的左(203)和右(204)端口的存储设备(201)包括存储体(401-0差分401-7),信号量逻辑(302) ,以及端口耦合电路(403,404,405-0,差异405-7,406-0,差异406-7,407-0,差异407-7)。 信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号(313,314),并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口 银行存取授权信号。 存储设备中还包括邮箱寄存器(2500-0L DIFFERENCE 2500-3L,2500-0R差分2500-3R),中断产生电路(2514-0L差分2514-3L,2514-0R差分2514-3R,2900 ,3000,307,308)以及中断状态和原因寄存器(3101L差分3102L,3101R差分3102R,3301L差分3302L,3301R差分3302R)。 左右电子设备使用邮箱寄存器相互发送消息,无需等待。 中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备,并且当消息已被写入其中一个邮箱寄存器时。 中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息,哪些邮箱寄存器包含用于它们的消息。
    • 40. 发明申请
    • SYSTEM AND METHOD FOR LONG RUNNING COMPUTE USING BUFFERS AS TIMESLICES
    • 使用缓冲区作为时间表长时间运行的系统和方法
    • US20130162661A1
    • 2013-06-27
    • US13333920
    • 2011-12-21
    • Jeffrey A. BolzJeff SmithJesse HallDavid SodmanPhilip CuadraNaveen Leekha
    • Jeffrey A. BolzJeff SmithJesse HallDavid SodmanPhilip CuadraNaveen Leekha
    • G06T1/00
    • G06T1/20G06F9/3802G06F9/3836
    • A system and method for using command buffers as timeslices or periods of execution for a long running compute task on a graphics processor. Embodiments of the present invention allow execution of long running compute applications with operating systems that manage and schedule graphics processing unit (GPU) resources and that may have a predetermined execution time limit for each command buffer. The method includes receiving a request from an application and determining a plurality of command buffers required to execute the request. Each of the plurality of command buffers may correspond to some portion of execution time or timeslice. The method further includes sending the plurality of command buffers to an operating system operable for scheduling the plurality of command buffers for execution on a graphics processor. The command buffers from a different request are time multiplexed within the execution of the plurality of command buffers on the graphics processor.
    • 使用命令缓冲区作为图形处理器上长时间运行的计算任务的执行时间或时间段的系统和方法。 本发明的实施例允许使用管理和调度图形处理单元(GPU)资源的操作系统执行长时间运行的计算应用,并且可以对每个命令缓冲器具有预定的执行时间限制。 该方法包括从应用程序接收请求并确定执行请求所需的多个命令缓冲区。 多个命令缓冲器中的每一个可以对应于执行时间或时间片的一部分。 该方法还包括将多个命令缓冲器发送到可操作用于调度多个命令缓冲器以在图形处理器上执行的操作系统。 来自不同请求的命令缓冲器在图形处理器上的多个命令缓冲器的执行中被时分复用。