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1. 发明申请

US20130162661A1 SYSTEM AND METHOD FOR LONG RUNNING COMPUTE USING BUFFERS AS TIMESLICES 审中-公开
标题翻译：使用缓冲区作为时间表长时间运行的系统和方法
公开(公告)号：US20130162661A1
公开(公告)日：2013-06-27
申请号：US13333920
申请日：2011-12-21
申请人： Jeffrey A. Bolz , Jeff Smith , Jesse Hall , David Sodman , Philip Cuadra , Naveen Leekha
发明人： Jeffrey A. Bolz , Jeff Smith , Jesse Hall , David Sodman , Philip Cuadra , Naveen Leekha
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/3802 , G06F9/3836
摘要： A system and method for using command buffers as timeslices or periods of execution for a long running compute task on a graphics processor. Embodiments of the present invention allow execution of long running compute applications with operating systems that manage and schedule graphics processing unit (GPU) resources and that may have a predetermined execution time limit for each command buffer. The method includes receiving a request from an application and determining a plurality of command buffers required to execute the request. Each of the plurality of command buffers may correspond to some portion of execution time or timeslice. The method further includes sending the plurality of command buffers to an operating system operable for scheduling the plurality of command buffers for execution on a graphics processor. The command buffers from a different request are time multiplexed within the execution of the plurality of command buffers on the graphics processor.
摘要翻译：使用命令缓冲区作为图形处理器上长时间运行的计算任务的执行时间或时间段的系统和方法。本发明的实施例允许使用管理和调度图形处理单元（GPU）资源的操作系统执行长时间运行的计算应用，并且可以对每个命令缓冲器具有预定的执行时间限制。该方法包括从应用程序接收请求并确定执行请求所需的多个命令缓冲区。多个命令缓冲器中的每一个可以对应于执行时间或时间片的一部分。该方法还包括将多个命令缓冲器发送到可操作用于调度多个命令缓冲器以在图形处理器上执行的操作系统。来自不同请求的命令缓冲器在图形处理器上的多个命令缓冲器的执行中被时分复用。

2. 发明授权

US08928677B2 Low latency concurrent computation 有权
标题翻译：低延迟并发计算
公开(公告)号：US08928677B2
公开(公告)日：2015-01-06
申请号：US13357569
申请日：2012-01-24
申请人： Daniel Elliot Wexler , Jeffrey A. Bolz , Jesse David Hall , Philip Alexander Cuadra , Naveen Leekha , Ignacio Llamas
发明人： Daniel Elliot Wexler , Jeffrey A. Bolz , Jesse David Hall , Philip Alexander Cuadra , Naveen Leekha , Ignacio Llamas
IPC分类号： G06F15/80 , G06T1/20
CPC分类号： G06F9/5027 , G06F2209/509
摘要： One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.
摘要翻译：本发明的一个实施例提出了一种用于在并行处理子系统上执行低等待时间计算的技术。低延迟功能节点暴露于操作系统。低延迟功能节点和通用功能节点被配置为针对并行处理子系统内的相同底层处理器资源。操作系统存储由与低延迟功能节点相关联的低延迟命令缓冲器内由用户应用产生的低延迟任务。并行处理子系统在完成在通用命令缓冲器中执行任务之前有利地执行来自低等待时间命令缓冲器的任务，从而减少低延迟任务的完成等待时间。

3. 发明申请

US20130187935A1 LOW LATENCY CONCURRENT COMPUTATION 有权
标题翻译：低期并发计算
公开(公告)号：US20130187935A1
公开(公告)日：2013-07-25
申请号：US13357569
申请日：2012-01-24
申请人： Daniel Elliot Wexler , Jeffrey A. Bolz , Jesse David Hall , Philip Alexander Cuadra , Naveen Leekha , Ignacio Llamas
发明人： Daniel Elliot Wexler , Jeffrey A. Bolz , Jesse David Hall , Philip Alexander Cuadra , Naveen Leekha , Ignacio Llamas
IPC分类号： G06F15/80
CPC分类号： G06F9/5027 , G06F2209/509
摘要： One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.
摘要翻译：本发明的一个实施例提出了一种用于在并行处理子系统上执行低等待时间计算的技术。低延迟功能节点暴露于操作系统。低延迟功能节点和通用功能节点被配置为针对并行处理子系统内的相同底层处理器资源。操作系统存储由与低延迟功能节点相关联的低延迟命令缓冲器内由用户应用产生的低延迟任务。并行处理子系统有利地在完成在通用命令缓冲器中执行任务之前从低延迟命令缓冲器执行任务，从而减少低延迟任务的完成等待时间。

4. 发明申请

US20110063318A1 Image Loads, Stores and Atomic Operations 审中-公开
标题翻译：图像负载，商店和原子操作
公开(公告)号：US20110063318A1
公开(公告)日：2011-03-17
申请号：US12855602
申请日：2010-08-12
申请人： Jeffrey A. Bolz , Patrick R. Brown
发明人： Jeffrey A. Bolz , Patrick R. Brown
IPC分类号： G06T11/40
CPC分类号： G06T15/005 , G06F13/1605 , G06T1/20 , G06T15/80 , G09G5/363
摘要： One embodiment of the present invention sets forth a method for accessing texture objects stored within a texture memory. The method comprises the steps of receiving a texture bind request from an application program, wherein the texture bind request includes an object identifier that identifies a first texture object stored in the texture memory and an image identifier that identifies a first image unit, binding the first texture object to the first image unit based on the texture bind request, receiving, within a shader engine, a first shading program command from the application program for performing a first memory access operation on the first texture object, wherein the memory access operation is a store operation or atomic operation to an arbitrary location in the image, and performing, within the shader engine, the first memory access operation on the first texture object via the first image unit.
摘要翻译：本发明的一个实施例提出了一种访问存储在纹理存储器内的纹理对象的方法。该方法包括以下步骤：从应用程序接收纹理绑定请求，其中纹理绑定请求包括识别存储在纹理存储器中的第一纹理对象的对象标识符和标识第一图像单元的图像标识符，纹理对象基于纹理绑定请求到第一图像单元，在着色器引擎内接收来自应用程序的第一着色程序命令，用于对第一纹理对象执行第一存储器访问操作，其中存储器访问操作是将操作或原子操作存储到图像中的任意位置，以及在着色引擎内，经由第一图像单元在第一纹理对象上执行第一存储器访问操作。

5. 发明授权

US09202303B2 System and method for compositing path color in path rendering 有权
标题翻译：在路径渲染中合成路径颜色的系统和方法
公开(公告)号：US09202303B2
公开(公告)日：2015-12-01
申请号：US13112874
申请日：2011-05-20
申请人： Jeffrey A. Bolz , Mark J. Kilgard
发明人： Jeffrey A. Bolz , Mark J. Kilgard
IPC分类号： G09G5/00 , G06T15/00 , G06T11/20
CPC分类号： G06T15/005 , G06T11/203
摘要： One embodiment of the present invention sets forth a technique for compositing a rendered path object into an image buffer. A shader program executing within a graphics processing unit (GPU) performs a stenciling operation for the path object and subsequently performs a texture barrier operation, which invalidates caches configured to store texture and frame buffer data within the GPU. The shader program then performs covering operation for the path object in which the shader renders color samples for the path object and composites the color samples into an image buffer. The shader program binds to the image buffer for access as both a texture map and a writeable image. Stencil values are reset when corresponding pixels are written once per path object, and texture caches are invalidated via the texture barrier operation, which is performed after each covering operation per path object.
摘要翻译：本发明的一个实施例提出了一种用于将渲染的路径对象合成到图像缓冲器中的技术。在图形处理单元（GPU）内执行的着色器程序执行路径对象的模板操作，并且随后执行纹理屏障操作，这使得被配置为在GPU内存储纹理和帧缓冲器数据的高速缓存无效。着色程序然后对路径对象执行覆盖操作，其中着色器为路径对象呈现颜色样本，并将颜色样本复合到图像缓冲区中。着色器程序绑定到图像缓冲区以作为纹理贴图和可写图像。当每个路径对象写入一次对应的像素时，模板值被复位，纹理高速缓存通过每个路径对象的每个覆盖操作之后执行的纹理屏障操作无效。

6. 发明申请

US20110242125A1 BINDLESS MEMORY ACCESS IN DIRECT 3D 有权
标题翻译：直接3D中的无痕记忆访问
公开(公告)号：US20110242125A1
公开(公告)日：2011-10-06
申请号：US13078848
申请日：2011-04-01
申请人： Jesse David HALL , Jeffrey A. Bolz
发明人： Jesse David HALL , Jeffrey A. Bolz
IPC分类号： G09G5/00 , G06T1/00
CPC分类号： G06T1/20
摘要： One embodiment of the present invention sets for a method for accessing data objects stored in a memory that is accessible by a graphics processing unit (GPU). The method comprises the steps of creating a data object in the memory based on a command received from an application program, transmitting a first handle associated with the data object to the application program such that data associated with different graphics commands can be accessed by the GPU, wherein the first handle includes a memory address that provides access to only a particular portion of the data object, receiving a first graphics command as well as the first handle from the application program, wherein the first graphics command includes a draw command or a compute grid launch, and transmitting the first graphics command and the first handle to the GPU for processing.
摘要翻译：本发明的一个实施例设置用于访问存储在由图形处理单元（GPU）可访问的存储器中的数据对象的方法。该方法包括以下步骤：基于从应用程序接收的命令在存储器中创建数据对象，将与数据对象相关联的第一句柄发送到应用程序，使得与GPU不同的图形命令相关联的数据可被GPU访问，其中所述第一句柄包括仅提供对所述数据对象的特定部分的访问的存储器地址，从所述应用程序接收第一图形命令以及所述第一句柄，其中所述第一图形命令包括绘制命令或计算网格发射，并将第一图形命令和第一个句柄传送到GPU进行处理。

7. 发明授权

US09245371B2 Global stores and atomic operations 有权
标题翻译：全球商店和原子营运
公开(公告)号：US09245371B2
公开(公告)日：2016-01-26
申请号：US12849766
申请日：2010-08-03
申请人： Jeffrey A. Bolz , Patrick R. Brown
发明人： Jeffrey A. Bolz , Patrick R. Brown
IPC分类号： G06T15/00 , G06T15/80 , G06T1/20 , G09G5/36 , G06F13/16
CPC分类号： G06T15/005 , G06F13/1605 , G06T1/20 , G06T15/80 , G09G5/363
摘要： One embodiment of the present invention sets forth a method for storing processed data within buffer objects stored in buffer object memory from within shader engines executing on a GPU. The method comprises the steps of receiving a stream of one or more shading program commands via a graphics driver, executing, within a shader engine, at least one of the one or more shading program commands to generate processed data, determining from the stream of one or more shading program commands an address associated with a first data object stored within the buffer memory, and storing, from within the shader engine, the processed data in the first data object stored within the buffer memory.
摘要翻译：本发明的一个实施例提出了一种用于在从GPU执行的着色器引擎内存储在缓冲器对象存储器中的缓冲器对象内存储经处理的数据的方法。该方法包括以下步骤：经由图形驱动器接收一个或多个阴影程序命令的流，在着色器引擎内执行一个或多个着色程序命令中的至少一个，以生成经处理的数据，从一个或更多的阴影程序命令与存储在缓冲存储器中的第一数据对象相关联的地址，以及从着色器引擎内存储处理的数据在存储在缓冲存储器内的第一数据对象中。

8. 发明授权

US08189009B1 Indexed access to texture buffer objects using a graphics library 有权
标题翻译：使用图形库索引对纹理缓冲区对象的访问
公开(公告)号：US08189009B1
公开(公告)日：2012-05-29
申请号：US11609859
申请日：2006-12-12
申请人： Patrick R. Brown , Jeffrey A. Bolz
发明人： Patrick R. Brown , Jeffrey A. Bolz
IPC分类号： G09G5/00 , G06T15/50 , G06T15/60
CPC分类号： G06T15/04 , G06T2200/28
摘要： A method for generating a texture buffer object configured for storing and manipulating texture data for graphics processing operations includes the steps of creating a buffer object configured to store the texture data, binding the buffer object to a texture buffer object, binding the texture buffer object to one of a plurality of texture targets included within a texture image unit, and binding a shader program to a processing unit within a graphics rendering pipeline. One advantage of the disclosed method is that, once a texture buffer object is bound as the target of a texture image unit, shader programs may read and/or write to the buffer object referenced by the texture buffer object, without having to rebind that texture buffer object.
摘要翻译：一种用于生成用于存储和操作用于图形处理操作的纹理数据的纹理缓冲对象的方法包括以下步骤：创建被配置为存储纹理数据的缓冲对象，将缓冲对象绑定到纹理缓冲对象，将纹理缓冲对象绑定到包括在纹理图像单元内的多个纹理目标中的一个，并将着色器程序绑定到图形渲染流水线内的处理单元。所公开方法的一个优点是，一旦纹理缓冲器对象被绑定为纹理图像单元的目标，着色器程序可以读取和/或写入由纹理缓冲器对象引用的缓冲器对象，而不必重新绑定该纹理缓冲对象。

9. 发明授权

US09437025B2 Stencil data compression system and method and graphics processing unit incorporating the same 有权
标题翻译：模板数据压缩系统及其结合的方法和图形处理单元
公开(公告)号：US09437025B2
公开(公告)日：2016-09-06
申请号：US13547362
申请日：2012-07-12
申请人： Jeffrey A. Bolz
发明人： Jeffrey A. Bolz
IPC分类号： G06T15/60 , G06T9/00 , G06T11/40
CPC分类号： G06T11/40 , G06T9/00 , G06T15/60 , G09G2340/02
摘要： A system and method for compressing stencil data attendant to rendering an image. In one embodiment, the method includes: (1) selecting a base stencil value for a particular group, (2) selecting a single-bit delta value for each sample in the particular group and (3) storing the stencil base value and the delta values in a frame buffer.
摘要翻译：一种压缩模板数据的系统和方法，用于渲染图像。在一个实施例中，该方法包括：（1）为特定组选择基本模板值，（2）为特定组中的每个样本选择单位增量值，以及（3）存储模版基础值和三角形帧缓冲区中的值。

10. 发明授权

US09324175B2 Memory coherency in graphics command streams and shaders 有权
标题翻译：图形命令流和着色器中的内存一致性
公开(公告)号：US09324175B2
公开(公告)日：2016-04-26
申请号：US12849701
申请日：2010-08-03
申请人： Jeffrey A. Bolz , Patrick R. Brown
发明人： Jeffrey A. Bolz , Patrick R. Brown
IPC分类号： G06T15/00 , G06T15/80 , G06T1/20 , G09G5/36 , G06F13/16
CPC分类号： G06T15/005 , G06F13/1605 , G06T1/20 , G06T15/80 , G09G5/363
摘要： One embodiment of the present invention sets forth a technique for performing a computer-implemented method that controls memory access operations. A stream of graphics commands includes at least one memory barrier command. Each memory barrier command in the stream of graphics command delays memory access operations scheduled for any command specified after the memory barrier command until all memory access operations scheduled for commands specified prior to the memory barrier command have completely executed.
摘要翻译：本发明的一个实施例提出了一种用于执行控制存储器访问操作的计算机实现的方法的技术。图形命令流包括至少一个存储器屏障命令。图形命令流中的每个存储器屏障命令延迟了在存储器屏障命令之后指定的任何命令调度的存储器访问操作，直到针对在存储器屏障命令之前指定的命令调度的所有存储器访问操作已经完全执行。

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