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31. 发明授权

US08222733B2 Semiconductor device package 有权
标题翻译：半导体器件封装
公开(公告)号：US08222733B2
公开(公告)日：2012-07-17
申请号：US12729034
申请日：2010-03-22
申请人： Ming-Hsiang Cheng , Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Ming-Hsiang Cheng , Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： H01L23/00 , H01L21/50
CPC分类号： H01L25/0652 , H01L23/053 , H01L25/50 , H01L2224/16225 , H01L2924/15311 , H01L2924/15331 , H01L2924/19105
摘要： A first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.
摘要翻译：第一基板具有面向第二基板的第二表面的第一表面。有源芯片设置在第一表面上并电连接到第一表面，并且间隔彼此间隔开，其中有源芯片分别具有第一有源表面。桥芯片机械地和电连接到第二表面，并且具有与有源芯片的第一有源表面部分地重叠的第二有源表面，使得桥接芯片用于提供有源芯片之间的邻近通信。连接结构设置在第一表面和第二表面之间，用于组合第一基板和第二基板。

32. 发明授权

US08115285B2 Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof 有权
标题翻译：具有保护层以提高表面安装及其制造方法的高级四边形扁平无铅芯片封装
公开(公告)号：US08115285B2
公开(公告)日：2012-02-14
申请号：US12192805
申请日：2008-08-15
申请人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
发明人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。每个引线包括上倾斜部分和下倾斜部分。芯片设置在腔体底部并耦合到引线。封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。保护层基本上覆盖至少一个引线的下倾斜部分和下表面。

33. 发明申请

US20110291690A1 Apparatus and Method for Testing Non-Contact Pads of a Semiconductor Device to be Tested 有权
标题翻译：用于测试要测试的半导体器件的非接触焊盘的装置和方法
公开(公告)号：US20110291690A1
公开(公告)日：2011-12-01
申请号：US12784121
申请日：2010-05-20
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , I.L. Lin , Ken Juang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , I.L. Lin , Ken Juang , Ming-Hsiang Cheng
IPC分类号： G01R31/26
CPC分类号： G01R1/0483 , G01R1/0466 , G01R31/2886
摘要： The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on to and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening. Whereby, the non-contact pads of the semiconductor device to be tested face but not in physically contact with the testing pads of the active chip, so as to test the proximity communication between the non-contact pads of the semiconductor device and the testing pads of the active chip.
摘要翻译：本发明涉及一种用于测试待测半导体器件的非接触焊盘的装置和方法。该装置包括绝缘体，至少一个测试模块和多个探针。绝缘体包括容纳腔，下开口和至少一个侧开口。侧开口与容纳腔和下开口连通。测试模块设置在侧开口中，每个测试模块包括电路板和有源芯片。有源芯片设置在电路板上并与电路板电连接。有源芯片具有暴露于容纳腔的多个测试焊盘。探针设置在下开口中。因此，要测试的半导体器件的非接触焊盘面对但不与有源芯片的测试焊盘物理接触，以便测试半导体器件的非接触焊盘与测试焊盘之间的接近连接的有源芯片。

34. 发明授权

US07964949B2 Tenon-and-mortise packaging structure 有权
标题翻译：榫眼包装结构
公开(公告)号：US07964949B2
公开(公告)日：2011-06-21
申请号：US12216637
申请日：2008-07-09
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
IPC分类号： H01L23/02
CPC分类号： H01L23/3107 , H01L25/03 , H01L25/16 , H01L2225/0652 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.
摘要翻译：提供包括载体和芯片的榫眼包装结构。载体具有与顶表面相对的顶表面和下表面。顶表面形成至少一个榫头突起，并且下表面形成对应于形状，尺寸和位置的榫头突起的榫槽，使得两个载体可以通过将榫头投影连接到彼此并且彼此连接相应的榫槽。榫头和榫槽分别具有导电部分。当榫头突起和榫槽彼此接合时，导电部分彼此电连接。至少一个芯片嵌入在载体中。芯片分别具有有源表面和背面，并与载体的顶表面和下表面电连接。

35. 发明申请

US20100200974A1 SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME 审中-公开
标题翻译：使用相同的半导体封装结构
公开(公告)号：US20100200974A1
公开(公告)日：2010-08-12
申请号：US12505071
申请日：2009-07-17
申请人： Chao-Fu Weng , Tsung-Yueh Tsai , Chang-Ying Hung , Jen-Chieh Kao
发明人： Chao-Fu Weng , Tsung-Yueh Tsai , Chang-Ying Hung , Jen-Chieh Kao
IPC分类号： H01L23/52 , H01L23/49 , H01L23/28
CPC分类号： H01L24/05 , H01L23/3121 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/0516 , H01L2224/05164 , H01L2224/05166 , H01L2224/05181 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/73265 , H01L2225/06506 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2924/00012
摘要： A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.
摘要翻译：提供了使用其的半导体封装结构。半导体封装结构包括第一半导体元件，第二半导体元件，绑定线和模制化合物。第一半导体元件包括半导体管芯和焊盘。焊盘设置在半导体管芯的上方，并且包括金属基底，设置在金属基底上方的硬金属层和设置在硬金属层上方的抗氧化金属层。硬质金属层的硬度大于金属基体的硬度。抗氧化金属层的活性低于硬质金属层的活性。第一半导体元件设置在第二半导体元件上方。接合线连接到焊盘和第二半导体元件。成型复合体密封第一半导体元件和接合线并覆盖第二半导体元件。

36. 发明授权

US07071553B2 Package structure compatible with cooling system 有权
标题翻译：封装结构兼容冷却系统
公开(公告)号：US07071553B2
公开(公告)日：2006-07-04
申请号：US10711237
申请日：2004-09-03
申请人： Tsung-Yueh Tsai , Sheng-Yang Peng
发明人： Tsung-Yueh Tsai , Sheng-Yang Peng
IPC分类号： H01L23/34
CPC分类号： H01L23/473 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L2924/09701 , H01L2924/00014 , H01L2924/00
摘要： The present invention relates to a package structure compatible with a cooling system, the package structure comprising a carrier, a chip, a mold compound and a cooling tubule that can be connected to a cooling system. The chip is arranged on the carrier and electrically connected to the carrier, while the mold compound covers the chip and one surface of the carrier. The cooling tubule is disposed either within the mold compound or on an outer surface of the mold compound. The cooling tubule is connected to a cooling tubing of the cooling system and a fluid driven by a pump circulates in the cooling tubing and the cooling tubule for heat dissipation.
摘要翻译：本发明涉及一种与冷却系统兼容的封装结构，该封装结构包括可连接到冷却系统的载体，芯片，模具化合物和冷却小管。芯片布置在载体上并电连接到载体上，而模具化合物覆盖芯片和载体的一个表面。冷却管被设置在模具化合物内或模具化合物的外表面上。冷却管与冷却系统的冷却管连接，由泵驱动的流体在冷却管和冷却管中循环，用于散热。

37. 发明申请

US20110309516A1 SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20110309516A1
公开(公告)日：2011-12-22
申请号：US12819796
申请日：2010-06-21
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/538 , H01L21/768 , H01L21/60
CPC分类号： H01L23/48 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/06513 , H01L2225/06531 , H01L2225/06541 , H01L2924/00014 , H01L2924/1815 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased.
摘要翻译：半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。半导体封装包括第一芯片和第二芯片。第一芯片包括第一有源表面，至少一个第一非顶部金属层和多个第一信号耦合焊盘。第一非顶部金属层设置成与第一有源表面相邻并间隔开第二距离。第一信号耦合焊盘设置在第一非顶部金属层上。第二芯片电连接到第一芯片。第二芯片包括第二有源表面，至少一个第二非顶部金属层和多个第三信号耦合焊盘。第二活性表面面向第一芯片的第一有效表面。第二非顶部金属层被布置成与第二有源表面相邻并且与第二有源表面间隔开第四距离。第三信号耦合焊盘设置在第二非顶部金属层上，并电容耦合到第一芯片的第一信号耦合焊盘，从而提供第一芯片与第二芯片之间的接近通信。由此，第一芯片的第一信号耦合焊盘与第二芯片的第三信号耦合焊盘之间的间隙变化受到第二距离和第四距离的严格控制。因此，半导体封装的批量生产量增加。

38. 发明申请

US20110298139A1 Semiconductor Package 审中-公开
标题翻译：半导体封装
公开(公告)号：US20110298139A1
公开(公告)日：2011-12-08
申请号：US12794390
申请日：2010-06-04
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/538 , H01L23/52
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3171 , H01L23/48 , H01L23/49816 , H01L23/5383 , H01L24/05 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L2224/0401 , H01L2224/16225 , H01L2224/16227 , H01L2224/48091 , H01L2224/4824 , H01L2224/731 , H01L2224/85 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01076 , H01L2924/014 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/30107 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the strength of the first chip and the second chip is increased after being mounted to the substrate, so the yield of the semiconductor package is increased.
摘要翻译：本发明涉及半导体封装。半导体封装包括衬底，第一芯片和第二芯片。衬底具有第一表面，第二表面和至少一个通孔。第一芯片设置在基板的第一表面附近。第一芯片包括第一有源表面和多个第一信号焊盘。第一活性表面的一部分暴露于通孔。第一信号垫的位置对应于通孔。第二芯片设置成与第二表面相邻。第二芯片包括第二有源表面和多个第二信号焊盘。第二活性表面的一部分暴露于通孔。第二信号焊盘的位置对应于通孔，并且第二信号焊盘电容耦合到第一芯片的第一信号焊盘，以便提供第一芯片和第二芯片之间的邻近通信。由此，第一芯片和第二芯片的强度在安装到基板之后增加，因此增加了半导体封装的成品率。

39. 发明申请

US20110227212A1 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件封装及其制造方法
公开(公告)号：US20110227212A1
公开(公告)日：2011-09-22
申请号：US12729034
申请日：2010-03-22
申请人： Ming-Hsiang CHENG , Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Ming-Hsiang CHENG , Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： H01L23/00 , H01L21/50
CPC分类号： H01L25/0652 , H01L23/053 , H01L25/50 , H01L2224/16225 , H01L2924/15311 , H01L2924/15331 , H01L2924/19105
摘要： A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a first substrate, a second substrate, two active chips, a bridge chip and a connection structure. The first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.
摘要翻译：公开了一种半导体器件封装及其制造方法。半导体器件封装包括第一衬底，第二衬底，两个有源芯片，桥芯片和连接结构。第一基板具有面向第二基板的第二表面的第一表面。有源芯片设置在第一表面上并电连接到第一表面，并且间隔彼此间隔开，其中有源芯片分别具有第一有源表面。桥芯片机械地和电连接到第二表面，并且具有与有源芯片的第一有源表面部分地重叠的第二有源表面，使得桥接芯片用于提供有源芯片之间的邻近通信。连接结构设置在第一表面和第二表面之间，用于组合第一基板和第二基板。

40. 发明申请

US20090230526A1 ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A PROTECTIVE LAYER TO ENHANCE SURFACE MOUNTING AND MANUFACTURING METHODS THEREOF 有权
标题翻译：高级四角平面无铅芯片包装有保护层，以增强表面安装及其制造方法
公开(公告)号：US20090230526A1
公开(公告)日：2009-09-17
申请号：US12192805
申请日：2008-08-15
申请人： Chien-Wen Chen , An-shih Tseng , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai
发明人： Chien-Wen Chen , An-shih Tseng , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。每个引线包括上倾斜部分和下倾斜部分。芯片设置在腔体底部并耦合到引线。封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。保护层基本上覆盖至少一个引线的下倾斜部分和下表面。

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