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31. 发明授权

US08947903B2 Memory chip with more than one type of memory cell 有权
标题翻译：内存芯片具有多种类型的内存单元
公开(公告)号：US08947903B2
公开(公告)日：2015-02-03
申请号：US13178021
申请日：2011-07-07
申请人： Cheng Hung Lee , XiuLi Yang , Liangbo Zhuang
发明人： Cheng Hung Lee , XiuLi Yang , Liangbo Zhuang
IPC分类号： G11C11/00 , G11C7/12 , G11C8/08 , G11C7/18
CPC分类号： G11C5/06 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/005
摘要： A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.
摘要翻译：一种半导体存储器芯片，其具有由相应的字线驱动器和位线驱动的字线，以将信号传送到具有位线和位线存储器单元的交叉处的存储器单元的各个位线放大器/驱动器。包括各种存储单元类型的半导体存储器芯片，基于字线和位线之间的交点的位置的交叉路口处的存储单元的类型。

32. 发明授权

US08587023B2 Guard rings with local coupling capacitance 有权
标题翻译：具有局部耦合电容的保护环
公开(公告)号：US08587023B2
公开(公告)日：2013-11-19
申请号：US11137241
申请日：2005-05-25
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： H01L29/74
CPC分类号： H01L21/765 , H01L27/0629 , H01L27/0921
摘要： A guard ring system is disclosed for protecting an integrated circuit comprising. It has a first guard ring area formed by a well in the substrate, a capacitor area formed within the first guard ring area which further includes two well contacts formed into the well and biased by a first supply voltage, and a dielectric layer placed between the two contacts on the well with its first side in contact with the well. A second supply voltage complementary to the first supply voltage is applied to a second side of the dielectric layer so that a voltage difference across the dielectric layer provides a local capacitance embedded therein.
摘要翻译：公开了用于保护集成电路的保护环系统，包括：它具有由衬底中的阱形成的第一保护环区域，形成在第一保护环区域内的电容器区域，其还包括形成在阱中并由第一电源电压偏置的两个阱触点，以及置于井的两个接触点，其第一面与井接触。与第一电源电压互补的第二电源电压被施加到电介质层的第二侧，使得跨介电层的电压差提供嵌入其中的局部电容。

33. 发明授权

US08411479B2 Memory circuits, systems, and methods for routing the memory circuits 有权
标题翻译：用于路由存储器电路的存储器电路，系统和方法
公开(公告)号：US08411479B2
公开(公告)日：2013-04-02
申请号：US12835041
申请日：2010-07-13
申请人： Cheng Hung Lee , Jui-Che Tsai , Ching-Wei Wu , Kuang Ting Chen
发明人： Cheng Hung Lee , Jui-Che Tsai , Ching-Wei Wu , Kuang Ting Chen
IPC分类号： G11C5/08
CPC分类号： G11C11/41 , G11C5/063 , G11C8/14 , G11C11/412 , H01L27/11 , H01L27/1104
摘要： A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.
摘要翻译：存储电路包括第一存储器阵列。第一存储器阵列包括用于存储第一数据的至少一个第一存储器单元。所述至少一个第一存储单元与第一字线和第二字线耦合。第二存储器阵列与第一存储器阵列耦合。第二存储器阵列包括用于存储第二数据的至少一个第二存储器单元。所述至少一个第二存储单元与第三字线和第四字线耦合。第一个字线与第三个字线相连。第一字线在第一存储器阵列中的第一字线的布线方向上与第三字线不对齐。

34. 发明授权

US08320163B2 Eight-transistor SRAM memory with shared bit-lines 有权
标题翻译：具有共享位线的八晶体管SRAM存储器
公开(公告)号：US08320163B2
公开(公告)日：2012-11-27
申请号：US12750430
申请日：2010-03-30
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： G11C11/00 , G11C8/16
CPC分类号： G11C8/16 , G11C11/412
摘要： An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged along a row direction. A first word-line is coupled to the first SRAM cell. A second word-line is coupled to the second SRAM cell. A read bit-line is coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction. A write bit-line is coupled to the first SRAM cell and the second SRAM cell.
摘要翻译：集成电路结构包括包括第一读取端口和第一写入端口的第一静态随机存取存储器（SRAM）单元; 以及包括第二读取端口和第二写入端口的第二SRAM单元。第一SRAM单元和第二SRAM单元位于同一行中并沿着行方向布置。第一字线耦合到第一SRAM单元。第二字线耦合到第二SRAM单元。读位线耦合到第一SRAM单元和第二SRAM单元，其中读位线在垂直于行方向的列方向上延伸。写位线耦合到第一SRAM单元和第二SRAM单元。

35. 发明申请

US20120213010A1 Asymmetric Sense Amplifier Design 有权
标题翻译：非对称检测放大器设计
公开(公告)号：US20120213010A1
公开(公告)日：2012-08-23
申请号：US13030722
申请日：2011-02-18
申请人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
发明人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
IPC分类号： G11C7/10 , G11C7/06 , H01L25/00
CPC分类号： G11C7/08 , G11C7/065
摘要： A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.
摘要翻译：电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。第二电容大于第一电容。

36. 发明授权

US07420854B2 SRAM device and operating method 有权
标题翻译： SRAM器件和操作方法
公开(公告)号：US07420854B2
公开(公告)日：2008-09-02
申请号：US11493345
申请日：2006-07-26
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： G11C7/10
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a buried insulation layer to make the Pwell a gate terminal; hence the buried insulation layer serves as a gate insulation for the parasitic transistor.
摘要翻译：公开了一种改进的SRAM单元及其操作方法。 SRAM单元包括至少四个原始晶体管，例如一对栅极晶体管和一对上拉晶体管。 SRAM单元还包括一对寄生晶体管，其通过与掩埋绝缘层下方的P阱接触以使P阱成为栅极端子而形成; 因此掩埋绝缘层用作寄生晶体管的栅极绝缘。

37. 发明申请

US20080175077A1 Novel write VCCMIN improvement scheme 有权
标题翻译：小写写VCCMIN改进方案
公开(公告)号：US20080175077A1
公开(公告)日：2008-07-24
申请号：US11654983
申请日：2007-01-18
申请人： Cheng Hung Lee , Hung-Jen Liao , Kun-Lung Chen
发明人： Cheng Hung Lee , Hung-Jen Liao , Kun-Lung Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A semiconductor memory is disclosed, which comprises a plurality of memory cells, at least one high voltage power supply (CVDD) line coupled to the plurality of memory cells for supplying power to the same, and at least one controllable discharging circuit coupled between the CVDD line and a complementary low voltage power supply (ground), wherein only during a write operation the controllable discharging circuit is turned on for discharging the CVDD line.
摘要翻译：公开了一种半导体存储器，其包括多个存储器单元，耦合到用于向其供电的多个存储单元的至少一个高压电源（CVDD）线以及耦合在CVDD之间的至少一个可控放电电路线路和互补的低压电源（接地），其中仅在写入操作期间，可控放电电路导通以排出CVDD线。

38. 发明申请

US20080025109A1 SRAM device and operating method 有权
公开(公告)号：US20080025109A1
公开(公告)日：2008-01-31
申请号：US11493345
申请日：2006-07-26
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： G11C7/10
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a buried insulation layer to make the Pwell a gate terminal; hence the buried insulation layer serves as a gate insulation for the parasitic transistor.

39. 发明授权

US08958232B2 Method and apparatus for read assist to compensate for weak bit 有权
标题翻译：用于读取辅助补偿弱点的方法和装置
公开(公告)号：US08958232B2
公开(公告)日：2015-02-17
申请号：US13437081
申请日：2012-04-02
申请人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
发明人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
IPC分类号： G11C17/00
CPC分类号： G11C7/12 , G11C7/067 , G11C11/412 , G11C11/419
摘要： A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
摘要翻译：记忆辅助装置包括检测电路和补偿电路。检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

40. 发明授权

US08634268B2 Memory circuit having decoding circuits and method of operating the same 有权
标题翻译：具有解码电路的存储电路及其操作方法
公开(公告)号：US08634268B2
公开(公告)日：2014-01-21
申请号：US12912971
申请日：2010-10-27
申请人： Cheng Hung Lee , Hsu-Shun Chen
发明人： Cheng Hung Lee , Hsu-Shun Chen
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C11/418
摘要： The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.
摘要翻译：本申请公开了一种存储器电路，其具有耦合到第一存储体并被配置为接收多个地址控制信号并且响应于多个地址控制信号产生第一多个小区选择信号的第一解码器，耦合到第二存储体并且被配置为接收多个反相地址控制信号，并响应于所述多个反相地址控制信号产生第二多个单元选择信号。存储器电路还具有耦合到第二解码器的地址控制信号缓冲器，并且被配置为将多个地址控制信号转换成多个反相地址控制信号。

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