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1. 发明申请

US20120014158A1 MEMORY DEVICES 审中-公开
标题翻译：内存设备
公开(公告)号：US20120014158A1
公开(公告)日：2012-01-19
申请号：US12838572
申请日：2010-07-19
申请人： Ching-Wei WU , Cheng Hung LEE , Kuang Ting CHEN
发明人： Ching-Wei WU , Cheng Hung LEE , Kuang Ting CHEN
IPC分类号： G11C17/12
CPC分类号： G11C17/12
摘要： A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time.
摘要翻译：存储器件包括晶体管阵列，多个位线和多条源极线。晶体管包括栅极，漏极和源极端子。栅极端子电耦合到字线。多个位线将电源连接到晶体管阵列的漏极端子，并且多个源极线将电源连接到晶体管阵列的源极端子。在待机模式期间，这些连接被激活，从而限制泄漏电流，而不会引起与存储器访问/周期时间下降有关的缺点。

2. 发明申请

US20110019458A1 MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ROUTING THE MEMORY CIRCUITS 有权
标题翻译：用于路由存储器电路的存储器电路，系统和方法
公开(公告)号：US20110019458A1
公开(公告)日：2011-01-27
申请号：US12835041
申请日：2010-07-13
申请人： Cheng Hung Lee , Jui-Che Tsai , Ching-Wei Wu , Kuang Ting Chen
发明人： Cheng Hung Lee , Jui-Che Tsai , Ching-Wei Wu , Kuang Ting Chen
IPC分类号： G11C5/06
CPC分类号： G11C11/41 , G11C5/063 , G11C8/14 , G11C11/412 , H01L27/11 , H01L27/1104
摘要： A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.
摘要翻译：存储电路包括第一存储器阵列。第一存储器阵列包括用于存储第一数据的至少一个第一存储器单元。所述至少一个第一存储单元与第一字线和第二字线耦合。第二存储器阵列与第一存储器阵列耦合。第二存储器阵列包括用于存储第二数据的至少一个第二存储器单元。所述至少一个第二存储单元与第三字线和第四字线耦合。第一个字线与第三个字线相连。第一字线在第一存储器阵列中的第一字线的布线方向上与第三字线不对齐。

3. 发明授权

US08411479B2 Memory circuits, systems, and methods for routing the memory circuits 有权
标题翻译：用于路由存储器电路的存储器电路，系统和方法
公开(公告)号：US08411479B2
公开(公告)日：2013-04-02
申请号：US12835041
申请日：2010-07-13
申请人： Cheng Hung Lee , Jui-Che Tsai , Ching-Wei Wu , Kuang Ting Chen
发明人： Cheng Hung Lee , Jui-Che Tsai , Ching-Wei Wu , Kuang Ting Chen
IPC分类号： G11C5/08
CPC分类号： G11C11/41 , G11C5/063 , G11C8/14 , G11C11/412 , H01L27/11 , H01L27/1104
摘要： A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.
摘要翻译：存储电路包括第一存储器阵列。第一存储器阵列包括用于存储第一数据的至少一个第一存储器单元。所述至少一个第一存储单元与第一字线和第二字线耦合。第二存储器阵列与第一存储器阵列耦合。第二存储器阵列包括用于存储第二数据的至少一个第二存储器单元。所述至少一个第二存储单元与第三字线和第四字线耦合。第一个字线与第三个字线相连。第一字线在第一存储器阵列中的第一字线的布线方向上与第三字线不对齐。

4. 发明申请

US20120213010A1 Asymmetric Sense Amplifier Design 有权
标题翻译：非对称检测放大器设计
公开(公告)号：US20120213010A1
公开(公告)日：2012-08-23
申请号：US13030722
申请日：2011-02-18
申请人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
发明人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
IPC分类号： G11C7/10 , G11C7/06 , H01L25/00
CPC分类号： G11C7/08 , G11C7/065
摘要： A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.
摘要翻译：电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。第二电容大于第一电容。

5. 发明授权

US08437210B2 Asymmetric sense amplifier design 有权
标题翻译：非对称放大器设计
公开(公告)号：US08437210B2
公开(公告)日：2013-05-07
申请号：US13030722
申请日：2011-02-18
申请人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
发明人： Ching-Wei Wu , Kuang Ting Chen , Cheng Hung Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/065
摘要： A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.
摘要翻译：电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。第二电容大于第一电容。

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