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31. 发明申请

US20100257498A1 INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT 有权
标题翻译：增量时序优化和放置
公开(公告)号：US20100257498A1
公开(公告)日：2010-10-07
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

32. 发明申请

US20090271752A1 Legalization of VLSI circuit placement with blockages using hierarchical row slicing 有权
标题翻译： VLSI电路放置合法化使用分层行分片
公开(公告)号：US20090271752A1
公开(公告)日：2009-10-29
申请号：US12108599
申请日：2008-04-24
申请人： Charles J. Alpert , Michael W. Dotson , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
发明人： Charles J. Alpert , Michael W. Dotson , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.
摘要翻译：在存在阻塞的情况下使逻辑单元的放置合法化的分级方法根据大小（大和小）选择性地将阻塞分类为至少两个不同的集合。可移动逻辑单元首先在大阻塞之间的粗略区域中重新定位，以消除单元和大阻塞之间的重叠，而不考虑小的阻塞（同时满足粗略区域的容量约束），然后将可移动逻辑单元重新定位在小的堵塞以消除所有的细胞重叠（同时满足精细区域的容量限制）。粗细区域可以是具有对应于设计的单个电路行高度的高度的放置区域的水平切片。细胞被重新定位，从最初的位置移动，保持线长和时序优化。合法化技术可以利用具有多个重定位阶段的多于两个级别的粒度。

33. 发明授权

US08909015B2 Composition for high strength loose tube type fiber optic cable with excellent flexibility and impact resistance 有权
标题翻译：高强度松套管型光缆的组成，具有优良的柔韧性和抗冲击性
公开(公告)号：US08909015B2
公开(公告)日：2014-12-09
申请号：US13551944
申请日：2012-07-18
申请人： Jeong-Eun Lim , Yu-Hyoung Lee , Gi-Joon Nam
发明人： Jeong-Eun Lim , Yu-Hyoung Lee , Gi-Joon Nam
IPC分类号： G02B6/44
CPC分类号： G02B6/443 , G02B6/441 , G02B6/4494 , C08F210/06 , C08F210/16 , C08F2500/12
摘要： Disclosed is a composition for a high strength loose tube type fiber optic cable with excellent flexibility and excellent impact resistance, which includes a polypropylene-polyethylene copolymer having a melt flow index (MFI) of 1.1 g/10 minutes to 3.0 g/10 minutes at 230° C. and a flexural modulus of 10,000 to 23,000 kg/cm2. A fiber optic cable including a loose tube formed with the composition for a high strength loose tube type fiber optic cable has excellent flexibility and impact resistance as well as excellent appearance.
摘要翻译：公开了一种具有优异柔软性和优异抗冲击性的高强度松套管式光纤电缆用组合物，其包括熔融流动指数（MFI）为1.1g / 10分钟至3.0g / 10分钟的聚丙烯 - 聚乙烯共聚物 230℃，挠曲模量为10,000〜23,000kg / cm 2。包含由高强度松套管式光纤电缆组合物形成的松套管的光缆具有优异的柔韧性和抗冲击性以及出色的外观。

34. 发明授权

US08495548B2 Multi-patterning lithography aware cell placement in integrated circuit design 失效
标题翻译：集成电路设计中的多图案化光刻感知单元放置
公开(公告)号：US08495548B2
公开(公告)日：2013-07-23
申请号：US13248711
申请日：2011-09-29
申请人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
发明人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。执行细胞运动的全局阶段。执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位在为IC设计制作最终布局之前。

35. 发明申请

US20100314152A1 MICRO COAXIAL CABLE FOR HIGH BENDING PERFORMANCE 有权
标题翻译：用于高弯曲性能的微型同轴电缆
公开(公告)号：US20100314152A1
公开(公告)日：2010-12-16
申请号：US12526023
申请日：2007-11-08
申请人： Chan-Yong Park , ll-Gun Seo , Gi-Joon Nam , Jung-Won Park , In-Ha Kim , Gun-Joo Lee , June-Sun Kim
发明人： Chan-Yong Park , ll-Gun Seo , Gi-Joon Nam , Jung-Won Park , In-Ha Kim , Gun-Joo Lee , June-Sun Kim
IPC分类号： H01B7/00 , H01B17/22
CPC分类号： H01B11/1821
摘要： The present invention relates to a micro coaxial cable with a high bending performance, comprising an inner conductor; an insulating layer configured to surround the inner conductor, and a helical winding conductor configured to surround the insulating layer and having an elongation of 1.5 to 4% and a pitch of 3.0 to 5.0 D.
摘要翻译：本发明涉及具有高弯曲性能的微同轴电缆，其包括内导体; 构造成围绕内导体的绝缘层，以及构造成围绕绝缘层并且具有1.5至4％的伸长率和3.0至5.0D的间距的螺旋缠绕导体。

36. 发明申请

US20080047732A1 Micro CoAxial Cable 有权
标题翻译：微型辅助电缆
公开(公告)号：US20080047732A1
公开(公告)日：2008-02-28
申请号：US11781494
申请日：2007-07-23
申请人： Chan-Yong Park , Gi-Joon Nam , Jung-Won Park , In-Ha Kim , June-Sun Kim , Il-Gun Seo , Gun-Joo Lee
发明人： Chan-Yong Park , Gi-Joon Nam , Jung-Won Park , In-Ha Kim , June-Sun Kim , Il-Gun Seo , Gun-Joo Lee
IPC分类号： H01B7/17
CPC分类号： H01B11/1869 , H01B11/12
摘要： A micro coaxial cable includes an inner conductor; an insulation layer having foaming cells and formed to surround the inner conductor; an over-foaming preventing layer formed to surround the insulation layer for the purpose of uniform forming of the foaming cells; a metal shield layer formed to surround the over-foaming preventing layer; and a protective coating layer formed to surround the metal shield layer. The over-foaming preventing layer restrains abnormal growth of foaming cells formed in the insulation layer such that the foaming cells are successively adjacently formed with uniform size. Due to the uniformity of foaming, the dielectric constant of the insulation layer is not locally different but uniform as a whole, thereby capable of improving transmission characteristics. In addition, the micro coaxial cable enables to transmit signals even at a high frequency transmission of GHz range, which was impossible in the prior art.
摘要翻译：微同轴电缆包括内导体; 具有发泡单元并形成为围绕所述内部导体的绝缘层; 为了均匀地形成发泡孔而形成为围绕绝缘层的过度发泡防止层; 形成为包围防止发泡层的金属屏蔽层; 以及形成为围绕金属屏蔽层的保护涂层。发泡防止层抑制在绝缘层中形成的发泡细胞的异常生长，使得发泡细胞相继形成均匀的尺寸。由于发泡的均匀性，绝缘层的介电常数并不是局部不同的，而是整体上均匀，从而能够改善传输特性。此外，微同轴电缆即使在GHz范围的高频率传输也能够传输信号，这在现有技术中是不可能的。

37. 发明申请

US20070044994A1 Communication cable having spacer integrated with separator therein 审中-公开
标题翻译：通信电缆，其中具有与分离器集成的间隔物
公开(公告)号：US20070044994A1
公开(公告)日：2007-03-01
申请号：US11511755
申请日：2006-08-28
申请人： Chan-Yong Park , Jong-Seb Baeck , Gi-Joon Nam , Woo-Yong Dong
发明人： Chan-Yong Park , Jong-Seb Baeck , Gi-Joon Nam , Woo-Yong Dong
IPC分类号： H01B7/00
CPC分类号： H01B11/06
摘要： A communication cable includes a separator prepared in the cable for preventing alien crosstalk, and at least one spacer integrally formed with the separator at a side of the separator contacting with an outside jacket. The spacer forms a protrusion protruded out on the cable, and this protrusion makes the transmission wires in the cable be spaced apart from adjacent cables. Thus, alien crosstalk generated due to proximity of other cables during high frequency signal transmission may be prevented.
摘要翻译：通信电缆包括在电缆中制备的用于防止外来串扰的分离器，以及与分离器一体形成的至少一个与外部护套接触的隔板一侧的间隔件。间隔件形成在电缆上突出的突起，并且该突起使电缆中的传输线与相邻电缆间隔开。因此，可以防止在高频信号传输期间由于其它电缆的接近而产生的外来串扰。

38. 发明授权

US06877040B1 Method and apparatus for testing routability 有权
标题翻译：用于测试可布线性的方法和装置
公开(公告)号：US06877040B1
公开(公告)日：2005-04-05
申请号：US09624716
申请日：2000-07-25
申请人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
发明人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
IPC分类号： G06F15/173
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.
摘要翻译：一种用于确定多个网络的路由可行性的方法和装置。每个网络具有一组或多个路由解决方案，其中每个解决方案指定网络所消耗的一个或多个路由资源。生成具有表示相应的净/解对对的变量的活力布尔函数。如果存在一组变量的值，使得每个网络的至少一个变量在逻辑上为真，那么活动函数为真。使用表示网络/解决方案对的变量生成排他性功能。如果存在变量的至少一组值，使得没有资源被使用超过预定数量的网络，则排他性功能是真实的。如果有一组变量的值，使用提供的解决方案，网络可以路由，以使活动和排他性功能都是真实的。

39. 发明申请

US20050015738A1 Latch placement technique for reduced clock signal skew 失效
标题翻译：锁定放置技术可减少时钟信号偏移
公开(公告)号：US20050015738A1
公开(公告)日：2005-01-20
申请号：US10621950
申请日：2003-07-17
申请人： Charles Alpert , Gary Ellis , Gi-Joon Nam , Paul Villarrubia
发明人： Charles Alpert , Gary Ellis , Gi-Joon Nam , Paul Villarrubia
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.
摘要翻译：一种设计集成电路的方法，包括执行放置算法以将一组对象放置在集成电路内。对象集包括锁存对象和非锁定对象。该算法使对象最小化时钟信号延迟，受限于锁存对象相对于非锁定对象的位置分布的位置分布。锁定对象和非锁定对象放置约束可能会限制被锁定的物体质心和未锁定的物体质心之间的差异。被锁定的物体质心等于每个被锁定物体的大小位置乘积之和除以每个锁定物体的大小之和。约束可能要求被锁定的物体质心和非锁定质心均等于所有物体的质心。

40. 发明申请

US20130086543A1 MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：集成电路设计中的多图形图形识别芯片布局
公开(公告)号：US20130086543A1
公开(公告)日：2013-04-04
申请号：US13248711
申请日：2011-09-29
申请人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
发明人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。执行细胞运动的全局阶段。执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位在为IC设计制作最终布局之前。

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