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1. 发明申请

US20130086543A1 MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：集成电路设计中的多图形图形识别芯片布局
公开(公告)号：US20130086543A1
公开(公告)日：2013-04-04
申请号：US13248711
申请日：2011-09-29
申请人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
发明人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。执行细胞运动的全局阶段。执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位在为IC设计制作最终布局之前。

2. 发明授权

US08495548B2 Multi-patterning lithography aware cell placement in integrated circuit design 失效
标题翻译：集成电路设计中的多图案化光刻感知单元放置
公开(公告)号：US08495548B2
公开(公告)日：2013-07-23
申请号：US13248711
申请日：2011-09-29
申请人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
发明人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。执行细胞运动的全局阶段。执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位在为IC设计制作最终布局之前。

3. 发明授权

US08458634B2 Latch clustering with proximity to local clock buffers 失效
标题翻译：锁定聚类，靠近本地时钟缓冲区
公开(公告)号：US08458634B2
公开(公告)日：2013-06-04
申请号：US12912919
申请日：2010-10-27
申请人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/62
摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
摘要翻译：一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。确定第一组多个群集锁存器中的多个组。添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

4. 发明申请

US20120110532A1 LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS 失效
标题翻译：对本地时钟缓冲器进行锁存的锁存器
公开(公告)号：US20120110532A1
公开(公告)日：2012-05-03
申请号：US12912919
申请日：2010-10-27
申请人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/62
摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
摘要翻译：一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。确定第一组多个群集锁存器中的多个组。添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

5. 发明申请

US20120297355A1 WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN 审中-公开
标题翻译：电路设计中的创新和保存
公开(公告)号：US20120297355A1
公开(公告)日：2012-11-22
申请号：US13112098
申请日：2011-05-20
申请人： Charles Jay Alpert , Gi-Joon Nam , Shyam Ramji , Jarrod Alexander Roy , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles Jay Alpert , Gi-Joon Nam , Shyam Ramji , Jarrod Alexander Roy , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的空白创建和保存的方法，系统和计算机程序产品。通过估计将设计的拥塞区域的拥塞值减少到阈值所需的空白量来形成第一估计。将一组虚拟填充单元添加到拥塞区域，其中添加虚拟填充单元组不会向拥塞区域添加实际空白单元，而是至少通过第一估计减少拥塞区域。虚拟填充单元组中的虚拟填充单元被替换为相应的真实填充单元。确定设计是否改进。当设计没有改进时，创建最终的布局解决方案。

6. 发明授权

US08108819B2 Object placement in integrated circuit design 有权
标题翻译：对象放置在集成电路设计中
公开(公告)号：US08108819B2
公开(公告)日：2012-01-31
申请号：US12420156
申请日：2009-04-08
申请人： Charles Jay Alpert , Gi-Joon Nam , Jarrod Alexander Roy , Natarajan Vishvanathan
发明人： Charles Jay Alpert , Gi-Joon Nam , Jarrod Alexander Roy , Natarajan Vishvanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/08
摘要： A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.
摘要翻译：在说明性实施例中提供了用于在集成电路设计中改进的对象放置的方法，系统和计算机可用程序产品。 IC设计包括电池，电池包括电子元件，电线和为IC的互连而定义的引脚。收到与设计相对应的初始放置。估计初始放置的特征，其可以包括初始放置区域中的拥塞，针密度或两者。在初始位置的一部分上进行变换，包括改善特征的区域。如果转换后的位置的特征有所改善，则会生成与转换的位置对应的最终位置。该变换可以是调整对象的大小，加权连接，聚集多个对象，缩短由线引导的路线以及在初始放置中矫正线中的弯曲的任何组合。

7. 发明申请

US20100262944A1 OBJECT PLACEMENT IN INTEGRATED CIRCUIT DESIGN 有权
标题翻译：集成电路设计中的对象放置
公开(公告)号：US20100262944A1
公开(公告)日：2010-10-14
申请号：US12420156
申请日：2009-04-08
申请人： Charles Jay Alpert , Gi-Joon Nam , Jarrod Alexander Roy , Natarajan Vishvanathan
发明人： Charles Jay Alpert , Gi-Joon Nam , Jarrod Alexander Roy , Natarajan Vishvanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/08
摘要： A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.
摘要翻译：在说明性实施例中提供了用于在集成电路设计中改进的对象放置的方法，系统和计算机可用程序产品。 IC设计包括电池，电池包括电子元件，电线和为IC的互连而定义的引脚。收到与设计相对应的初始放置。估计初始放置的特征，其可以包括初始放置区域中的拥塞，针密度或两者。在初始位置的一部分上进行变换，包括改善特征的区域。如果转换后的位置的特征有所改善，则会生成与转换的位置对应的最终位置。该变换可以是调整对象的大小，加权连接，聚集多个对象，缩短由线引导的路线以及在初始放置中矫正线中的弯曲的任何组合。

8. 发明授权

US07020861B2 Latch placement technique for reduced clock signal skew 失效
标题翻译：锁定放置技术可减少时钟信号偏移
公开(公告)号：US07020861B2
公开(公告)日：2006-03-28
申请号：US10621950
申请日：2003-07-17
申请人： Charles Jay Alpert , Gary Robert Ellis , Gi-Joon Nam , Paul Gerard Villarrubia
发明人： Charles Jay Alpert , Gary Robert Ellis , Gi-Joon Nam , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.
摘要翻译：一种设计集成电路的方法，包括执行放置算法以将一组对象放置在集成电路内。对象集包括锁存对象和非锁定对象。该算法使对象最小化时钟信号延迟，受限于锁存对象相对于非锁定对象的位置分布的位置分布。锁定对象和非锁定对象放置约束可能会限制被锁定的物体质心和未锁定的物体质心之间的差异。被锁定的物体质心等于每个被锁定物体的大小位置乘积之和除以每个锁定物体的大小之和。约束可能要求被锁定的物体质心和非锁定质心均等于所有物体的质心。

9. 发明授权

US07073144B2 Stability metrics for placement to quantify the stability of placement algorithms 有权
标题翻译：放置的稳定性指标来量化放置算法的稳定性
公开(公告)号：US07073144B2
公开(公告)日：2006-07-04
申请号：US10825148
申请日：2004-04-15
申请人： Charles Jay Alpert , Gi-Joon Nam , Paul Gerard Villarrubia , Mehmet Can Yildiz
发明人： Charles Jay Alpert , Gi-Joon Nam , Paul Gerard Villarrubia , Mehmet Can Yildiz
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations between the layouts. The stability value can be normalized based on cell locations in a random placement. One stability metric measures absolute movement of individual cells in the layouts, weighted by cell area. The cell movements can be squared in calculating the stability value. Another stability metric measures the relative movement of cells with respect to their nets. Shifting of cells and symmetric reversal of cells about a net center does not contribute to this relative movement, but spreading of cells and rotation of cells with respect to the net center does contribute to the relative movement. Relative cell movements can again be squared in calculating the stability value. Many different layouts can be designed using the same placement tool with a range of different input parameters and different movement metrics to build a collection of comparative values that can be used to identify stability characteristics for that tool.
摘要翻译：一种评估用于设计集成电路芯片的物理布局的放置工具的稳定性的方法，通过使用具有不同输入参数集合的放置工具构造不同的单元布局，以及基于相应的运动来计算稳定性值单元格位置之间的布局。稳定性值可以根据随机位置中的单元格位置进行归一化。一个稳定度度量衡量单元格在布局中的绝对运动，由单元格区域加权。在计算稳定性值时，单元格移动可以平方。另一个稳定度量度衡量细胞相对于网的相对运动。细胞的移位和细胞对网络中心的对称反转对这种相对运动没有贡献，但是细胞的扩散和细胞的相对于网络中心的旋转确实有助于相对运动。在计算稳定性值时，相对单元移动可以再次平方。可以使用具有一系列不同输入参数和不同运动度量的相同放置工具来设计许多不同的布局，以构建可用于识别该工具的稳定性特征的比较值集合。

10. 发明授权

US07296252B2 Clustering techniques for faster and better placement of VLSI circuits 有权
标题翻译：用于更快更好地布置VLSI电路的聚类技术
公开(公告)号：US07296252B2
公开(公告)日：2007-11-13
申请号：US10996293
申请日：2004-11-22
申请人： Charles Jay Alpert , Gi-Joon Nam , Sherief Mohamed Reda , Paul Gerard Villarrubia
发明人： Charles Jay Alpert , Gi-Joon Nam , Sherief Mohamed Reda , Paul Gerard Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F17/50
摘要： A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects into a cluster based on the clustering scores, partitioning the objects as clustered and ungrouping the cluster after partitioning. The pair of objects having the highest clustering score are grouped into the cluster, and the clustering score is directly proportional to the total weight of connections between the two objects in the respective pair. The clustering scores are preferably inserted in a binary heap to identify the highest clustering score. After grouping, the clustering score for any neighboring object of a clustered object is marked to indicate that the clustering score is invalid and must be recalculated. The calculating and grouping are then repeated iteratively based on the previous clustered layout. Cluster growth can be controlled indirectly, or controlled directly by imposing an upper bound on cluster size.
摘要翻译：一种用于通过基于给定对中的两个对象的连接和两个对象的大小的布局来计算布局中的不同对对象的聚类分数来设计集成电路的布局的布局技术，然后将至少一个对对象基于聚类分数进入群集，将对象分区为群集，并在分区后取消分组群集。具有最高聚类分数的一对对象被分组到聚类中，并且聚类分数与相应对中的两个对象之间的连接的总权重成正比。聚类分数优选插入二进制堆中以识别最高聚类分数。分组后，将聚类对象的任何邻近对象的聚类分数标记为表示聚类分数无效并且必须重新计算。然后基于先前的聚类布局迭代地重复计算和分组。群集增长可以间接控制，也可以通过对群集大小施加上限直接控制。

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