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1. 发明授权

US07306977B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07306977B1
公开(公告)日：2007-12-11
申请号：US10651808
申请日：2003-08-29
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： H01L21/82
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

2. 发明授权

US07979816B1 Method and apparatus for implementing a circuit design for an integrated circuit 有权
标题翻译：用于实现集成电路的电路设计的方法和装置
公开(公告)号：US07979816B1
公开(公告)日：2011-07-12
申请号：US12100313
申请日：2008-04-09
申请人： Arne S. Barras , Rajeev Jayaraman
发明人： Arne S. Barras , Rajeev Jayaraman
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.
摘要翻译：描述了用于实现集成电路的电路设计的方法和装置。在一个示例中，利用至少一个设计工具处理电路设计的第一版本（408）。对于至少一个设计工具捕获统计数据（410），并响应于统计数据自动调整其操作属性（420）。对所述电路设计的第二版本进行处理（422），所述至少一个设计工具具有调整的操作属性。在另一示例中，电路设计在第一次迭代中使用至少一个设计工具进行处理（506）。针对所述至少一个设计工具捕获统计数据（508），并响应于所述第一次迭代的统计数据自动调整其操作属性（514）以进行第二次迭代。电路设计被重新处理（516），其中至少一个设计工具在第二次迭代中具有调整的操作属性。

3. 发明授权

US06289496B1 Placement of input-output design objects into a programmable gate array supporting multiple voltage standards 失效
标题翻译：将输入输出设计对象放置在支持多个电压标准的可编程门阵列中
公开(公告)号：US06289496B1
公开(公告)日：2001-09-11
申请号：US09107022
申请日：1998-06-29
申请人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
发明人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
IPC分类号： G06F1750
CPC分类号： H03K19/17744 , G06F17/5072 , H03K19/17788
摘要： A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
摘要翻译：一种用于放置到具有不同电压标准的输入输出（I / O）设计对象的可编程门阵列中的方法和装置。可编程门阵列具有多个位置，其布置成支撑具有多个不同输入和输出电压标准的接口的支架。在示例性实施例中，I / O设计对象通过首先执行模拟退火而被放置在可编程门阵列的IOB中，该模拟退火考虑了放置在IOB中的设计对象电压标准之间的冲突。然后，使用模拟退火的放置结果进行二分相匹配。最后，如果二分配匹配不能产生可行的布局，则基于先前的布局结果将标准分配给银行，并重复二分配匹配过程。

4. 发明授权

US07725868B1 Method and apparatus for facilitating signal routing within a programmable logic device 有权
标题翻译：用于促进可编程逻辑器件内的信号路由的方法和装置
公开(公告)号：US07725868B1
公开(公告)日：2010-05-25
申请号：US11983550
申请日：2007-11-09
申请人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
发明人： Vinay Verma , Anirban Rahut , Sudip K. Nag , Jason H. Anderson , Rajeev Jayaraman
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H01L27/0207 , G06F17/5027 , G06F17/5077 , H01L27/11803
摘要： Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.
摘要翻译：描述了在具有路由资源的可编程逻辑设备内促进信号路由的方法和装置。在一个示例中，路由资源被形成为其中对于每个组的路由资源是相同类型的组。这些组中的一组通过能够与一对组的另一组中的至少一个其他路由资源电连接的一组组中的至少一个路由资源的关联相关联。

5. 发明授权

US07185299B1 Methods of estimating routing delays during the placement process in programmable logic devices 有权
标题翻译：在可编程逻辑器件中的放置过程中估计路由延迟的方法
公开(公告)号：US07185299B1
公开(公告)日：2007-02-27
申请号：US10354810
申请日：2003-01-30
申请人： Rajeev Jayaraman
发明人： Rajeev Jayaraman
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072 , G06F2217/84
摘要： Methods of estimating routing delays between two points in a programmable logic device (PLD). The invention takes advantage of the fact that there are a finite number of possible routes (routing paths) between any two points in a PLD. In PLDs with a regular and tiled structure, such as field programmable gate arrays, the number of routes between any two points that are likely to be used by the router is relatively small. Thus, given the locations of the two points to be connected, the route most likely to be used by the router can be determined, and an associated delay can be calculated. This associated delay is then reported as the estimated routing delay. This method of delay estimation can be much more accurate than using an average delay. When the delays between possible paths vary widely, the actual delay of a connection can vary widely from the average.
摘要翻译：估计可编程逻辑器件（PLD）中两点之间路由延迟的方法。本发明利用了在PLD中的任何两个点之间存在有限数量的可能路由（路由路径）的事实。在具有常规和平铺结构的PLD（例如现场可编程门阵列）中，路由器可能使用的任何两个点之间的路由数目相对较少。因此，考虑到要连接的两个点的位置，可以确定路由器最有可能使用的路由，并且可以计算相关的延迟。然后将该相关延迟报告为估计的路由延迟。这种延迟估计方法可以比使用平均延迟更准确。当可能路径之间的延迟变化很大时，连接的实际延迟可能与平均值有很大差异。

6. 发明授权

US07380219B1 Method and apparatus for implementing a circuit design for an integrated circuit 有权
标题翻译：用于实现集成电路的电路设计的方法和装置
公开(公告)号：US07380219B1
公开(公告)日：2008-05-27
申请号：US11054862
申请日：2005-02-10
申请人： Arne S. Barras , Rajeev Jayaraman
发明人： Arne S. Barras , Rajeev Jayaraman
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.
摘要翻译：描述了用于实现集成电路的电路设计的方法和装置。在一个示例中，利用至少一个设计工具处理电路设计的第一版本（408）。对于至少一个设计工具捕获统计数据（410），并响应于统计数据自动调整其操作属性（420）。对所述电路设计的第二版本进行处理（422），所述至少一个设计工具具有调整的操作属性。在另一示例中，电路设计在第一次迭代中使用至少一个设计工具进行处理（506）。针对所述至少一个设计工具捕获统计数据（508），并响应于所述第一次迭代的统计数据自动调整其操作属性（514）以进行第二次迭代。电路设计被重新处理（516），其中至少一个设计工具在第二次迭代中具有调整的操作属性。

7. 发明授权

US06877040B1 Method and apparatus for testing routability 有权
标题翻译：用于测试可布线性的方法和装置
公开(公告)号：US06877040B1
公开(公告)日：2005-04-05
申请号：US09624716
申请日：2000-07-25
申请人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
发明人： Gi-Joon Nam , Sandor S. Kalman , Jason H. Anderson , Rajeev Jayaraman , Sudip K. Nag , Jennifer Zhuang
IPC分类号： G06F15/173
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.
摘要翻译：一种用于确定多个网络的路由可行性的方法和装置。每个网络具有一组或多个路由解决方案，其中每个解决方案指定网络所消耗的一个或多个路由资源。生成具有表示相应的净/解对对的变量的活力布尔函数。如果存在一组变量的值，使得每个网络的至少一个变量在逻辑上为真，那么活动函数为真。使用表示网络/解决方案对的变量生成排他性功能。如果存在变量的至少一组值，使得没有资源被使用超过预定数量的网络，则排他性功能是真实的。如果有一组变量的值，使用提供的解决方案，网络可以路由，以使活动和排他性功能都是真实的。

8. 发明授权

US06625795B1 Method and apparatus for placement of input-output design objects into a programmable gate array 有权
标题翻译：用于将输入输出设计对象放置到可编程门阵列中的方法和装置
公开(公告)号：US06625795B1
公开(公告)日：2003-09-23
申请号：US09866052
申请日：2001-05-25
申请人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
发明人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , H03K19/17744
摘要： A method and apparatus for placement into a programmable gate array of I/O design objects having different I/O attributes. The I/O attributes of an I/O design object define the electrical characteristics of the design object. The programmable gate array has a plurality of sites (IOBs) arranged into banks supporting a variety of electrical interface characteristics. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between I/O attributes of I/O design objects as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, sets of I/O attributes are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
摘要翻译：一种用于放置到具有不同I / O属性的I / O设计对象的可编程门阵列中的方法和装置。 I / O设计对象的I / O属性定义了设计对象的电气特性。可编程门阵列具有布置成支持各种电接口特性的单元的多个位置（IOB）。在示例实施例中，I / O设计对象通过首先执行模拟退火而被放置到可编程门阵列的IOB中，该模拟退火考虑了放置在IOB中的I / O设计对象的I / O属性之间的冲突。然后，使用模拟退火的放置结果进行二分相匹配。最后，如果二分配匹配不能产生可行的布局，那么根据先前的放置结果，将一组I / O属性分配给存储体，并重复二分配匹配过程。

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