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31. 发明授权

US06500677B2 Method for fabricating a ferroelectric memory configuration 失效
标题翻译：铁电存储器配置的制造方法
公开(公告)号：US06500677B2
公开(公告)日：2002-12-31
申请号：US10027106
申请日：2001-12-26
申请人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
发明人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.
摘要翻译：本发明提供了一种方法。在制造铁电存储器结构的方法的第一步骤中，提供了具有多个存储单元的衬底。每个存储单元具有至少一个选择晶体管，至少一个短路晶体管和至少一个铁电电容器。晶体管以导电方式连接到铁电电容器的第一电极。在下一步骤中，施加至少一个电绝缘层。在下一步骤中，产生用于连接铁电电容器的第二电极的至少一个接触孔。接下来，制造用于连接短路晶体管的接触孔。接下来，接触孔填充有导电材料。接下来，施加导电层并图案化，使得强电介质电容器的第二电极分别与短路晶体管导通。

32. 发明授权

US06487128B2 Integrated memory having memory cells and reference cells, and operating method for such a memory 有权
标题翻译：具有存储单元和参考单元的集成存储器以及用于这种存储器的操作方法
公开(公告)号：US06487128B2
公开(公告)日：2002-11-26
申请号：US09962411
申请日：2001-09-24
申请人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/14
摘要： The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
摘要翻译：存储器具有相同构造的存储器单元和参考单元。通过经由第一开关元件将读取放大器的参考单元解耦，并且经由第二开关元件将连接到参考单元的位线的一部分电连接到电位线，将参考信息项写入参考单元携带参考信息。

33. 发明授权

US06452852B2 Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration 有权
标题翻译：具有刷新逻辑电路的半导体存储器配置和刷新半导体存储器配置的存储器内容的方法
公开(公告)号：US06452852B2
公开(公告)日：2002-09-17
申请号：US09767380
申请日：2001-01-22
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C11/406
摘要： In a semiconductor memory configuration, a refresh operation is always started by a refresh logic circuit when a comparison circuit determines that there is a specific minimum difference when comparing a characteristic variable of at least one reference memory cell with a reference value (VREF).
摘要翻译：在半导体存储器配置中，当比较电路确定在将至少一个参考存储单元的特征变量与参考值（VREF）进行比较时确定存在特定最小差异时，刷新逻辑电路总是开始刷新操作。

34. 发明授权

US06351422B2 Integrated memory having a differential sense amplifier 有权
标题翻译：具有差分读出放大器的集成存储器
公开(公告)号：US06351422B2
公开(公告)日：2002-02-26
申请号：US09820235
申请日：2001-03-28
申请人： Thomas Röhr , Thomas Böhm , Heinz Hönigschmid , Georg Braun
发明人： Thomas Röhr , Thomas Böhm , Heinz Hönigschmid , Georg Braun
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/12 , G11C7/22
摘要： The memory has writable memory cells. In addition, it has a bit line pair which connects the memory cells MC to a differential sense amplifier. A control unit is used for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.
摘要翻译：内存有可写存储单元。此外，它具有将存储单元MC连接到差分读出放大器的位线对。控制单元用于在存储器单元之一导通地连接到用于读访问操作的位线之一之前的多个步骤中对位线进行预充电。对于写访问操作，在读出放大器将数据传送到位线对之前，控制单元执行不超过为读访问操作提供的一些位线预充电步骤。

35. 发明授权

US6157561A Integrated circuit memory with low resistance, segmented power supply lines 有权
标题翻译：具有低电阻，分段电源线的集成电路存储器
公开(公告)号：US6157561A
公开(公告)日：2000-12-05
申请号：US513587
申请日：2000-02-25
申请人： Tobias Schlager , Georg Braun , Heinz Hoenigschmid , Thomas Boehm
发明人： Tobias Schlager , Georg Braun , Heinz Hoenigschmid , Thomas Boehm
IPC分类号： G11C5/06 , H01L21/8242
CPC分类号： H01L27/10882 , G11C5/063
摘要： An integrated memory having a first wiring plane with parallel conductor tracks running therein. A second wiring plane in the memory has segments running in it that are parallel to the conductor tracks. Word lines are each formed by a conductor track of a first type and by segments configured parallel to this conductor track. A conductor track of a second type is connected to a first supply line and to regions that are configured in a third wiring plane within the cell array.
摘要翻译：一种集成存储器，其具有在其中延伸的并行导体轨迹的第一布线平面。存储器中的第二布线平面具有平行于导体轨迹的线段。字线各自由第一类型的导体轨道和与该导体轨道平行配置的段形成。第二类型的导体轨道连接到第一电源线以及配置在电池阵列内的第三布线平面中的区域。

36. 发明授权

US6137712A Ferroelectric memory configuration 有权
标题翻译：铁电存储器配置
公开(公告)号：US6137712A
公开(公告)日：2000-10-24
申请号：US440818
申请日：1999-11-15
申请人： Thomas Rohr , Heinz Honigschmid , Georg Braun
发明人： Thomas Rohr , Heinz Honigschmid , Georg Braun
IPC分类号： G11C14/00 , G11C11/22
CPC分类号： G11C11/22
摘要： The invention relates to a memory configuration comprising a multiplicity of memory cells. Each of the memory cells has at least one ferroelectric storage capacitor and a selection transistor. The memory cells are addressed via word lines and bit line pairs. It is possible for a reference signal obtained from a reference cell pair via a bit line pair to be compared with a read signal from a memory cell in a sense amplifier. The sense amplifier is thereby assigned two bit line pairs connected in such a way that the reference signal is applied via the first bit line pair and, at the same time, the read signal is applied via the second bit line pair to the sense amplifier.
摘要翻译：本发明涉及包括多个存储单元的存储器配置。每个存储单元具有至少一个铁电存储电容器和选择晶体管。存储单元通过字线和位线对寻址。可以将从参考单元对经由位线对获得的参考信号与来自读出放大器中的存储单元的读取信号进行比较。因此，读出放大器被分配两个位线对，其连接方式是经由第一位线对施加参考信号，并且同时经由第二位线对将读取信号施加到读出放大器。

37. 发明授权

US07936201B2 Apparatus and method for providing a signal for transmission via a signal line 有权
标题翻译：用于提供用于经由信号线传输的信号的装置和方法
公开(公告)号：US07936201B2
公开(公告)日：2011-05-03
申请号：US11644998
申请日：2006-12-22
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： G06F5/06
CPC分类号： G06F13/1668
摘要： An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.
摘要翻译：一种用于经由信号线提供用于传输的信号的装置包括控制器电路，其具有用于指示信号线是否将处于非活动状态的信号的输出和耦合到控制器电路的开关电路，并且具有耦合到信号线。如果信号指示信号线处于非活动状态，则输出在不同的信号电平之间切换。

38. 发明申请

US20100074038A1 Memory Dies for Flexible Use and Method for Configuring Memory Dies 有权
标题翻译：用于灵活使用的内存模式和配置内存模块的方法
公开(公告)号：US20100074038A1
公开(公告)日：2010-03-25
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10 , H01L21/66 , H01L23/538
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译：公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

39. 发明授权

US07457174B2 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted 有权
标题翻译：半导体存储器和方法，用于在接收要发送的写入数据期间适配时钟信号和选通信号之间的相位关系
公开(公告)号：US07457174B2
公开(公告)日：2008-11-25
申请号：US11410320
申请日：2006-04-24
申请人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
发明人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.
摘要翻译：提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

40. 发明授权

US07447805B2 Buffer chip and method for controlling one or more memory arrangements 有权
标题翻译：用于控制一个或多个存储器布置的缓冲器芯片和方法
公开(公告)号：US07447805B2
公开(公告)日：2008-11-04
申请号：US10792408
申请日：2004-03-03
申请人： Georg Braun , Hermann Ruckerbauer
发明人： Georg Braun , Hermann Ruckerbauer
IPC分类号： G06F13/00 , G06F13/38 , G06F3/00 , G06F5/00 , G06F12/00
CPC分类号： G06F13/1673 , G06F12/0215 , G06F12/0862 , G06F2212/6022
摘要： A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.
摘要翻译：一种具有第一数据接口的缓冲器芯片，用于接收要写入的数据项，并且用于发送已经被读取的数据项，具有用于并行化所接收的数据项的转换单元，并且用于串行化要发送的数据项，具有用于经由存储器数据总线将并行化数据项写入存储器装置的第二数据接口，以及用于经由存储器数据总线接收从存储器装置读取的数据项; 具有用于缓冲存储要写入的数据项的写缓冲存储器，具有按顺序具有控制单元，在接收到要经由第一数据接口写入的数据项以符合写命令之后，中断在随后的读取命令时，经由第二数据接口从写缓冲存储器写入的数据。

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