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31. 发明授权

US09041105B2 Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure 有权
标题翻译：集成电路包括绝缘体上绝缘体上的晶体管结构，相关方法和设计结构
公开(公告)号：US09041105B2
公开(公告)日：2015-05-26
申请号：US13553947
申请日：2012-07-20
申请人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
发明人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/088 , H01L27/12 , H01L21/84 , H01L21/265
CPC分类号： H01L27/1203 , H01L21/84
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

32. 发明授权

US08618583B2 Junction gate field effect transistor structure having n-channel 有权
标题翻译：具有n沟道的结栅场效应晶体管结构
公开(公告)号：US08618583B2
公开(公告)日：2013-12-31
申请号：US13108305
申请日：2011-05-16
申请人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/66 , H01L21/70 , H01L21/337
CPC分类号： H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
摘要： The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
摘要翻译：本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。

33. 发明申请

US20140021547A1 INTEGRATED CIRCUIT INCLUDING TRANSISTOR STRUCTURE ON DEPLETED SILICON-ON-INSULATOR, RELATED METHOD AND DESIGN STRUCTURE 有权
标题翻译：集成电路，包括在绝缘体上的晶体管结构，相关方法和设计结构
公开(公告)号：US20140021547A1
公开(公告)日：2014-01-23
申请号：US13553947
申请日：2012-07-20
申请人： William F. Clark, JR. , Qizhi Liu , Robert M. Rassel , Yun Shi
发明人： William F. Clark, JR. , Qizhi Liu , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/088 , H01L21/265
CPC分类号： H01L27/1203 , H01L21/84
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

34. 发明授权

US07670889B2 Structure and method for fabrication JFET in CMOS 失效
标题翻译： CMOS中制造JFET的结构和方法
公开(公告)号：US07670889B2
公开(公告)日：2010-03-02
申请号：US12132638
申请日：2008-06-04
申请人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/337 , H01L21/84
CPC分类号： H01L29/8086 , H01L29/66901
摘要： A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.
摘要翻译：更具体地，涉及用于制造SOI中的JFET的设计结构，JFET和制造JFET的方法。 JFET包括直接在SOI层上形成的栅极多晶硅，并且栅极氧化层插入在栅极多晶硅和SOI层的外边缘之间。

35. 发明申请

US20090302355A1 STRUCTURE, STRUCTURE AND METHOD FOR FABRICATION JFET IN CMOS 失效
标题翻译： CMOS中的制造JFET的结构，结构和方法
公开(公告)号：US20090302355A1
公开(公告)日：2009-12-10
申请号：US12132638
申请日：2008-06-04
申请人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/808 , H01L21/337 , G06F17/50
CPC分类号： H01L29/8086 , H01L29/66901
摘要： A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.
摘要翻译：更具体地，涉及用于制造SOI中的JFET的设计结构，JFET和制造JFET的方法。 JFET包括直接在SOI层上形成的栅极多晶硅，并且栅极氧化层插入在栅极多晶硅和SOI层的外边缘之间。

36. 发明申请

US20120292669A1 FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US20120292669A1
公开(公告)日：2012-11-22
申请号：US13108305
申请日：2011-05-16
申请人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
摘要： The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
摘要翻译：本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。

37. 发明授权

US07977201B2 Methods for forming back-end-of-line resistive semiconductor structures 有权
标题翻译：形成后端电阻半导体结构的方法
公开(公告)号：US07977201B2
公开(公告)日：2011-07-12
申请号：US12191633
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L21/20
CPC分类号： H01L23/5228 , H01L21/76816 , H01L23/5226 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。覆盖第一金属线的第二电介质层的一部分是使用光致抗蚀剂凹陷的，而第二金属线作为蚀刻掩模。在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

38. 发明授权

US07804124B2 Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory 失效
标题翻译：用于非易失性随机存取存储器的存储器单元的装置结构和用于非易失性随机存取存储器的设计结构
公开(公告)号：US07804124B2
公开(公告)日：2010-09-28
申请号：US12118241
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.
摘要翻译：非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。半导体本体包括源极，漏极以及源极和漏极之间的沟道。浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。第一电介质层设置在半导体本体的沟道和浮栅之间。第二介电层设置在控制栅电极和浮栅电极之间。

39. 发明申请

US20100230732A1 FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC 有权
标题翻译：具有气隙介质的场效应晶体管
公开(公告)号：US20100230732A1
公开(公告)日：2010-09-16
申请号：US12547529
申请日：2009-08-26
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , WiIliam R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , WiIliam R. Tonti , Yun Shi
IPC分类号： H01L29/772 , H01L21/336 , H01L21/30
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

40. 发明授权

US08399927B2 Semiconductor structure including a high performance fet and a high voltage fet on an SOI substrate 有权
标题翻译：包括在SOI衬底上的高性能fet和高电压fet的半导体结构
公开(公告)号：US08399927B2
公开(公告)日：2013-03-19
申请号：US13367646
申请日：2012-02-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/148
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

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