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31. 发明授权

US5726931A DRAM with open digit lines and array edge reference sensing 失效
公开(公告)号：US5726931A
公开(公告)日：1998-03-10
申请号：US804182
申请日：1997-02-20
申请人： Paul S. Zagar , Mirmajid Seyyedy
发明人： Paul S. Zagar , Mirmajid Seyyedy
IPC分类号： G11C11/401 , G11C7/14 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C11/24 , G11C7/00 , G11C7/02
CPC分类号： G11C7/18 , G11C11/4097 , G11C11/4099 , G11C7/14
摘要： A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical characteristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.

32. 发明授权

US5696732A Burst EDO memory device 失效
标题翻译： Burst EDO存储设备
公开(公告)号：US5696732A
公开(公告)日：1997-12-09
申请号：US754780
申请日：1996-11-21
申请人： Paul S. Zagar , Brett L. Williams
发明人： Paul S. Zagar , Brett L. Williams
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
摘要翻译：集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。地址选通信号用于锁存第一个地址。在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。

33. 发明授权

US5666323A Synchronous NAND DRAM architecture 失效
标题翻译：同步NAND DRAM架构
公开(公告)号：US5666323A
公开(公告)日：1997-09-09
申请号：US615527
申请日：1996-03-11
申请人： Paul S. Zagar
发明人： Paul S. Zagar
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/4076 , G11C11/4096 , G11C8/00
CPC分类号： G11C11/4076 , G11C11/404 , G11C11/4045 , G11C11/4096 , G11C7/1039 , G11C7/1042 , G11C7/1072
摘要： An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual bank architecture and synchronous timing. The NAND structured memory cells provide an extremely dense memory array for a high capacity memory device. The input clock signal driving a synchronous word line generator provides a simplified high speed access to the array. A set of random access storage registers temporarily store data from the array and provide high speed page access to an entire page of data from each bank of the memory. The ability to access one bank while simultaneously opening or closing a row in the other bank allows for an unlimited number of high speed sequential data accesses.
摘要翻译：集成电路存储器件具有两组NAND结构的存储器单元和用于同步地锁存控制，地址和数据信号的时钟输入。通过使用双存储体架构和同步定时，对NAND结构中的顺序访问和恢复存储器位的时间延迟进行掩蔽。 NAND结构化存储器单元为高容量存储器件提供非常密集的存储器阵列。驱动同步字线发生器的输入时钟信号提供对阵列的简化的高速访问。一组随机访问存储寄存器临时存储阵列中的数据，并提供从存储器的每个存储体的整个数据页面的高速页面访问。在同时打开或关闭另一个行中的一行时访问一个存储体的能力允许无限数量的高速顺序数据访问。

34. 发明授权

US5384500A Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes 失效
标题翻译：可编程逻辑器件宏单元，具有排他反馈和独特的外部输入线，用于组合模式，并可容纳两个单独的可编程或平面
公开(公告)号：US5384500A
公开(公告)日：1995-01-24
申请号：US171865
申请日：1993-12-22
申请人： Mark A. Hawes , Paul S. Zagar
发明人： Mark A. Hawes , Paul S. Zagar
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17708
摘要： A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD. Exactly, this PLD can disable the I/O pad and still have an internal feedback to its logic circuitry.
摘要翻译：公开了一种具有输出宏单元电路的可编程逻辑器件（PLD）。具体地说，有一个宏单元具有专用逻辑信号反馈线和独占的外部输入信号线，两者都输入到PLD的输入端。确切地说，这个PLD可以禁用I / O焊盘，并且仍然有一个内部的反馈给它的逻辑电路。

35. 发明授权

US5270587A CMOS logic cell for high-speed, zero-power programmable array logic devices 失效
标题翻译： CMOS逻辑单元，用于高速，零功率可编程阵列逻辑器件
公开(公告)号：US5270587A
公开(公告)日：1993-12-14
申请号：US817167
申请日：1992-01-06
申请人： Paul S. Zagar
发明人： Paul S. Zagar
IPC分类号： H03K19/173 , H03K19/177 , H03K19/094 , G06F7/38
CPC分类号： H03K19/1736 , H03K19/17712
摘要： A CMOS logic cell, which may be readily arrayed to construct fast, zero-power programmable array logic (PAL) devices or field-programmable logic array (FPLAs) is disclosed. The cell is constructed from first and second pairs of P-channel insulated-gate field effect transistors (IGFETs), and first and second pairs of N-channel IGFETs. Each pair of P-channel IGFETS is connected in series between an output node and V.sub.cc, while each pair of N-channel IGFETS is connected in series between the output node and V.sub.ss. The gate of one transistor of the first. P-channel IGFET pair is connected to the output of a first memory cell, while the gate of the other transistor of the same pair is connected to an input signal I; the gate of one transistor of the second P-channel IGFET pair is connected to the output of a second memory cell, while the gate of the other transistor of the same pair is connected to signal I* (the complement of input signal I). Likewise, the gate of one transistor of the first N-channel IGFET pair is connected to the output of the first memory cell, while the gate of the other transistor of the same pair is connected to signal I*; the gate of one transistor of the second N-channel IGFET pair is connected to the output of the second memory cell, while the gate of the other transistor of the same pair is connected to signal I. Each of the memory cells may be programmed to provide either a CMOS logical 1 or 0 output, and may be either nonvolatile or volatile.
摘要翻译：公开了可以容易地排列以构建快速零功率可编程阵列逻辑（PAL）器件或现场可编程逻辑阵列（FPGA）的CMOS逻辑单元。该单元由第一和第二对P沟道绝缘栅场效应晶体管（IGFET）以及第一和第二对N沟道IGFET构成。每对P沟道IGFETS串联连接在输出节点和Vcc之间，而每对N沟道IGFETS串联连接在输出节点和Vss之间。第一个晶体管的栅极。 P沟道IGFET对连接到第一存储单元的输出，同一对的另一晶体管的栅极连接到输入信号I; 第二P沟道IGFET对的一个晶体管的栅极连接到第二存储单元的输出，而同一对的另一个晶体管的栅极连接到信号I *（输入信号I的补码）。类似地，第一N沟道IGFET对的一个晶体管的栅极连接到第一存储单元的输出，同一对的另一个晶体管的栅极连接到信号I *; 第二N沟道IGFET对的一个晶体管的栅极连接到第二存储单元的输出，而同一对的另一个晶体管的栅极连接到信号I.每个存储单元可被编程为提供CMOS逻辑1或0输出，并且可以是非易失性的或易失性的。

36. 发明授权

US5235221A Field programmable logic array with speed optimized architecture 失效
标题翻译：具有速度优化架构的现场可编程逻辑阵列
公开(公告)号：US5235221A
公开(公告)日：1993-08-10
申请号：US865007
申请日：1992-04-08
申请人： Kurt P. Douglas , Paul S. Zagar , Varadarajan L. Narasimhan
发明人： Kurt P. Douglas , Paul S. Zagar , Varadarajan L. Narasimhan
IPC分类号： H03K19/177
CPC分类号： H03K19/17708
摘要： A programmable logic device (PLD) is disclosed for finding a sum of products or other logic equations. Specifically, there is a PLD which has: 1) a programmable logical AND and programmable logical OR arrays/matrices, similar to a field programmable logic array; and 2) the fully programmable OR array has an optimized signal speed path and non-optimized signal speed path.
摘要翻译：公开了可编程逻辑器件（PLD），用于找到乘积和其他逻辑方程的总和。具体来说，有一个PLD，它具有：1）与现场可编程逻辑阵列类似的可编程逻辑与和可编程逻辑OR阵列/矩阵; 和2）完全可编程OR阵列具有优化的信号速度路径和未优化的信号速度路径。

37. 发明授权

US06597054B1 Reduced pitch laser redundancy fuse bank structure 有权
标题翻译：减少节距激光冗余熔丝库结构
公开(公告)号：US06597054B1
公开(公告)日：2003-07-22
申请号：US09140498
申请日：1998-08-27
申请人： Kirk Prall , Tod S. Stone , Paul S. Zagar
发明人： Kirk Prall , Tod S. Stone , Paul S. Zagar
IPC分类号： H01L2900
CPC分类号： G11C29/785 , G11C29/80 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.
摘要翻译：公开了一种用于激光熔丝排的配置，其中可用空间被更有效地使用。放置渐变宽度和可变配置的保险丝放置在最小化保险丝之间的平均距离并使熔丝密度最大化。或者，将公共源添加到标准激光熔丝结构中，使得其与保险丝相交，并且可用熔丝的数量加倍。

38. 发明授权

US06208568B1 Circuit for cancelling and replacing redundant elements 有权
标题翻译：用于取消和更换冗余元件的电路
公开(公告)号：US06208568B1
公开(公告)日：2001-03-27
申请号：US09133714
申请日：1998-08-13
申请人： Paul S. Zagar , Adrian E. Ong
发明人： Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C1300
CPC分类号： G11C29/785 , G11C29/838
摘要： In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.
摘要翻译：在具有可寻址主要元件的集成电路和可编程为替代主要元件的冗余元件中，提供了用于取消和替换冗余元件的电路和方法。描述了可以用于存储器中的电路，例如动态随机存取存储器（DRAM），其使用可选择地可吹出的反熔丝来禁用先前被编程为替换有缺陷的主要元件的冗余元件。本公开描述了一种用于永久地消除有缺陷的冗余元件并用另一个冗余元件替换有缺陷的冗余元件的方法。

39. 再颁专利

USRE36821E Wordline driver circuit having a directly gated pull-down device 失效
标题翻译：字线驱动电路具有直接门控下拉装置
公开(公告)号：USRE36821E
公开(公告)日：2000-08-15
申请号：US644351
申请日：1996-05-10
申请人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
发明人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
摘要翻译：本发明是用于快速驱动未选择的字线以纠正电位的电路和方法。本发明通过由解码电路产生的初级选择预解码信号直接选通的驱动装置将未选择的字线驱动到低电位。驱动装置电插入字线和参考节点之间。本发明提供低功率操作，并且为电源电压低于5伏的电路提供可靠的字线选择。

40. 发明授权

US5831918A Circuit and method for varying a period of an internal control signal during a test mode 失效
公开(公告)号：US5831918A
公开(公告)日：1998-11-03
申请号：US663939
申请日：1996-06-14
申请人： Todd A. Merritt , Paul S. Zagar
发明人： Todd A. Merritt , Paul S. Zagar
IPC分类号： G11C29/02 , G11C29/50 , G11C29/00
CPC分类号： G11C29/028 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C11/401 , G11C2029/5004
摘要： The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a period of an internal control signal to stress the DRAM during a test mode.

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