专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20120319163A1 SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE BIPOLAR TRANSISTOR AND DIODE 有权
标题翻译：半导体器件，包括绝缘栅双极晶体管和二极管
公开(公告)号：US20120319163A1
公开(公告)日：2012-12-20
申请号：US13495051
申请日：2012-06-13
申请人： Yukio TSUZUKI , Hiromitsu Tanabe , Kenji Kouno
发明人： Yukio TSUZUKI , Hiromitsu Tanabe , Kenji Kouno
IPC分类号： H01L27/06
CPC分类号： H01L21/263 , H01L29/1095 , H01L29/32 , H01L29/7397 , H01L29/861
摘要： A semiconductor device includes an IGBT forming region and a diode forming region. The IGBT forming region includes an IGBT operating section that operates as an IGBT and a thinned-out section that does not operate as an IGBT. The IGBT operating section includes a channel region, and the thinned-out section includes a first anode region. The diode forming region includes a second anode region. When an area density is defined as a value calculated by integrating a concentration profile of second conductivity type impurities in each of the channel region, the first anode region, and the second anode region in a depth direction, an area density of the channel region is higher than an area density of the first anode region and an area density of the second anode region.
摘要翻译：半导体器件包括IGBT形成区域和二极管形成区域。 IGBT形成区域包括作为IGBT工作的IGBT工作部和不作为IGBT工作的稀疏部。 IGBT操作部分包括沟道区，并且所述稀疏部包括第一阳极区。二极管形成区域包括第二阳极区域。当区域密度定义为通过在深度方向上积分沟道区域，第一阳极区域和第二阳极区域中的每一个中的第二导电类型杂质的浓度分布而计算出的值时，沟道区域的面积密度为高于第一阳极区域的面积密度和第二阳极区域的面积密度。

32. 发明申请

US20110260212A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110260212A1
公开(公告)日：2011-10-27
申请号：US13090288
申请日：2011-04-20
申请人： Yukio Tsuzuki , Kenji Kouno
发明人： Yukio Tsuzuki , Kenji Kouno
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696
摘要： An insulated gate semiconductor device includes a semiconductor substrate, a drift layer on the substrate, a base layer on the drift layer, a ring-shaped gate trench dividing the base layer into a channel layer and a floating layer, an emitter region located in the channel layer to be in contact with a side surface of the gate trench, a well region located on the periphery of a cell area of the base layer and having a depth greater than a depth of the base layer, and a ring-shaped buffer trench located adjacent to and spaced from the gate trench in a length direction of the gate trench. An edge of the well region is located in an area enclosed by the buffer trench in the length direction of the gate trench.
摘要翻译：绝缘栅极半导体器件包括半导体衬底，衬底上的漂移层，漂移层上的基极层，将基极层划分成沟道层和浮动层的环形栅极沟槽，位于沟道层与栅极沟槽的侧表面接触，位于基底层的单元区域的周边上并且具有大于基底层的深度的深度的阱区，以及环形缓冲沟槽位于栅极沟槽的长度方向附近并与栅极沟槽间隔开。阱区域的边缘位于由栅极沟槽的长度方向上的缓冲沟槽包围的区域中。

33. 发明授权

US07999314B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07999314B2
公开(公告)日：2011-08-16
申请号：US12213469
申请日：2008-06-19
申请人： Yukio Tsuzuki , Makoto Asai
发明人： Yukio Tsuzuki , Makoto Asai
IPC分类号： H01L29/66 , H01L21/336 , H01L21/8234 , H01L29/772 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7806
摘要： A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.
摘要翻译：半导体器件包括具有主侧和后侧的n导电型半导体衬底，布置在衬底的主侧上的p导电型层，以p导电型布置的主侧n导电型区域层，布置在基板的后侧上的后侧n导电型层，到达基板并穿透主侧n导电型区域和p导电型层的第一沟槽，到达基板的第二沟槽在p导电型层的内部，嵌入在第二沟槽中并连接到p导电型层的第二电极层。因此，可以获得其中二极管电池的恢复特性可以在不损害MOS晶体管单元或IGBT单元的性能而不损坏浪涌耐受性的情况下得到的半导体器件。

34. 发明申请

US20100156506A1 Semiconductor device including insulated gate bipolar transistor and diode 有权
标题翻译：半导体器件包括绝缘栅双极晶体管和二极管
公开(公告)号：US20100156506A1
公开(公告)日：2010-06-24
申请号：US12654228
申请日：2009-12-15
申请人： Yukio Tsuzuki , Hiromitsu Tanabe , Kenji Kouno
发明人： Yukio Tsuzuki , Hiromitsu Tanabe , Kenji Kouno
IPC分类号： H03K17/60 , H01L27/06
CPC分类号： H01L27/0664 , H01L29/0619 , H01L29/0834 , H01L29/7395 , H01L29/7397 , H03K17/0828 , H03K17/145
摘要： A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions.
摘要翻译：半导体器件包括半导体衬底中的垂直IGBT和垂直续流二极管。在半导体衬底的第一表面侧部分设置有多个基极区域，并且多个集电极区域和多个阴极区域交替地设置在半导体衬底的第二表面侧部分中。基极区域包括在垂直IGBT处于工作状态时设置通道的多个区域。半导体衬底的第一侧部分包括多个IGBT区域，每个IGBT区域各自位于相邻的两个沟道之间，包括与发射极电气耦合的一个基极区域，并与阴极区域中的一个相对。 IGBT区域包括多个窄区域和多个宽区域。

35. 发明授权

US07692214B2 Semiconductor device having IGBT cell and diode cell and method for designing the same 有权
标题翻译：具有IGBT单元和二极管单元的半导体器件及其设计方法
公开(公告)号：US07692214B2
公开(公告)日：2010-04-06
申请号：US11885334
申请日：2007-03-20
申请人： Norihito Tokura , Yukio Tsuzuki , Kenji Kouno
发明人： Norihito Tokura , Yukio Tsuzuki , Kenji Kouno
IPC分类号： H01L29/00
CPC分类号： H01L29/7395 , H01L27/0664 , H01L29/861
摘要： A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ρ1 and a thickness L1 of the first layer, a resistivity ρ2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (ρ1/ρ2)×(L1·L2/W22)
摘要翻译：半导体器件包括：半导体衬底; IGBT单元; 和二极管单元。衬底包括在第一表面上的第一层，相邻地布置在衬底的第二表面上的第二层和第三层以及在第一层和第二层和第三层之间的第四层。第一层提供了IGBT单元和二极管单元的漂移层。第二层提供IGBT单元的集电极层。第三层提供二极管单元的一个电极连接层。第一层的电阻率和第一层的厚度L1，第四层的电阻率rgr2和厚度L2以及第二层在基板平面上的最小宽度W2的一半具有（＆rgr ; 1 /＆rgr; 2）×（L1·L2 / W22）<1.6。

36. 发明授权

US07622768B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07622768B2
公开(公告)日：2009-11-24
申请号：US11110826
申请日：2005-04-21
申请人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
发明人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/511 , H01L29/66348 , H01L29/7397
摘要： On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.
摘要翻译：在氮化硅膜的表面上形成热氧化膜，然后在其上形成CVD氧化膜，以提供两层结构膜的氧化硅膜。此外，将两层结构膜的总厚度设定为5nm〜30nm的值。因此，将氧化硅膜制成热氧化膜和CVD氧化物膜的两层结构膜，从而实现氧化硅膜的厚度。结果，可以通过电荷陷阱现象防止Vth降低，并且防止由于氧化硅膜的鸟喙长度的增大而导致的Vth波动。

37. 发明授权

US07456484B2 Semiconductor device having IGBT and diode 失效
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US07456484B2
公开(公告)日：2008-11-25
申请号：US11648894
申请日：2007-01-03
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L21/00
CPC分类号： H01L29/7395 , H01L27/0664 , H01L29/0834 , H01L29/66333 , H01L29/861
摘要： A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.
摘要翻译：半导体器件包括：具有第一和第二半导体层的半导体衬底; IGBT，其具有集电极区域，第一半导体层中的基极区域，基极区域中的发射极区域和发射极区域与第一半导体层之间的基极区域中的沟道区域; 在所述第一半导体层中具有阳极区域的二极管和所述第一半导体层上的阴极电极; 和电阻区域。集电极区域和第二半导体层设置在第一半导体层上。用于增加第二半导体层的电阻的电阻区域通过绕过集电极区域而被布置在通过第一半导体层和第二半导体层的沟道区域和阴极电极之间的电流通路中。

38. 发明申请

US20070158680A1 Semiconductor device having IGBT and diode 失效
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US20070158680A1
公开(公告)日：2007-07-12
申请号：US11648894
申请日：2007-01-03
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/74
CPC分类号： H01L29/7395 , H01L27/0664 , H01L29/0834 , H01L29/66333 , H01L29/861
摘要： A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.
摘要翻译：半导体器件包括：具有第一和第二半导体层的半导体衬底; IGBT，其具有集电极区域，第一半导体层中的基极区域，基极区域中的发射极区域和发射极区域与第一半导体层之间的基极区域中的沟道区域; 在所述第一半导体层中具有阳极区域和在所述第一半导体层上的阴极电极的二极管; 和电阻区域。集电极区域和第二半导体层设置在第一半导体层上。用于增加第二半导体层的电阻的电阻区域通过绕过集电极区域而被布置在通过第一半导体层和第二半导体层的沟道区域和阴极电极之间的电流通路中。

39. 发明申请

US20050236664A1 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050236664A1
公开(公告)日：2005-10-27
申请号：US11110826
申请日：2005-04-21
申请人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
发明人： Takaaki Aoki , Mikimasa Suzuki , Yukio Tsuzuki , Tomofusa Shiga
IPC分类号： H01L29/78 , H01L21/331 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/511 , H01L29/66348 , H01L29/7397
摘要： On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.
摘要翻译：在氮化硅膜的表面上形成热氧化膜，然后在其上形成CVD氧化膜，以提供两层结构膜的氧化硅膜。此外，将两层结构膜的总厚度设定为5nm〜30nm的值。因此，将氧化硅膜制成热氧化膜和CVD氧化物膜的两层结构膜，从而实现氧化硅膜的厚度。结果，可以通过电荷陷阱现象防止Vth降低，并且防止由于氧化硅膜的鸟喙长度的增大而导致的Vth波动。

40. 发明申请

US20050090060A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050090060A1
公开(公告)日：2005-04-28
申请号：US10974838
申请日：2004-10-28
申请人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式