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31. 发明申请

WO2007109046A2 CROSS-POINT MEMORY ARRAY 审中-公开
标题翻译：交叉点记忆阵列
公开(公告)号：WO2007109046A2
公开(公告)日：2007-09-27
申请号：PCT/US2007/006425
申请日：2007-03-14
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert
发明人： SUTARDJA, Pantas , WU, Albert
IPC分类号： H01L27/24 , G11C16/02
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141
摘要： A phase-change memory (PCM) system comprises a PCM cell array that comprises a plurality of PCM cells. Each of the PCM cells includes diode arranged adjacent to a metallization layer; a heater element arranged adjacent to the diode, and a phase-change material arranged adjacent to the heater element.
摘要翻译：相变存储器（PCM）系统包括包括多个PCM单元的PCM单元阵列。每个PCM单元包括邻近金属化层布置的二极管; 与二极管相邻布置的加热器元件，以及邻近加热器元件设置的相变材料。

32. 发明申请

WO2007084749A2 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 审中-公开
标题翻译：闪存中错误校正的方法和系统
公开(公告)号：WO2007084749A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/001620
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD. , RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
发明人： RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

33. 发明申请

WO2014066462A2 APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS 审中-公开
标题翻译：用于改造电阻记忆细胞的装置和方法
公开(公告)号：WO2014066462A2
公开(公告)日：2014-05-01
申请号：PCT/US2013/066303
申请日：2013-10-23
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , LEE, Winston , LEE, Peter , CHANG, Runzi
发明人： SUTARDJA, Pantas , WU, Albert , LEE, Winston , LEE, Peter , CHANG, Runzi
IPC分类号： G11C29/50
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/00 , G11C13/0033 , G11C13/004 , G11C29/50008 , G11C2013/0076 , G11C2013/0083
摘要： A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.
摘要翻译：存储器包括存储器单元阵列，第一模块和第二模块。第一模块被配置为将存储器单元的第一状态与参考进行比较。存储单元位于存储单元的阵列中。第二模块被配置为在存储器单元的读取周期或写入周期之后并且基于该比较，改变存储器单元以调整存储器单元的第一状态和第二状态之间的差异。

34. 发明申请

WO2014062562A1 CONFIGURING RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY FOR WRITE OPERATIONS 审中-公开
标题翻译：配置电阻随机访问存储器（RRAM）阵列进行写操作
公开(公告)号：WO2014062562A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064819
申请日：2013-10-14
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C2013/0073 , G11C2213/79 , G11C2213/82
摘要： A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction.
摘要翻译：系统包括电阻随机存取存储单元和驱动电路。电阻性随机存取存储单元包括电阻元件和开关元件，并且具有连接到位线的第一端子和连接到字线的第二端子。驱动器电路被配置为响应于使用字线选择电阻性随机存取存储器单元，将第一极性的第一电压施加到位线，以通过引起电流将电阻性随机存取存储器单元编程为第一状态沿着第一方向流过电阻元件，并向位线流过第二极性的第二电压，以通过使电流沿第二方向流过电阻元件而将电阻性随机存取存储器单元编程为第二状态。

35. 发明申请

WO2014062558A1 SYSTEMS AND METHODS FOR READING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS 审中-公开
标题翻译：用于读取电阻随机存取存储器（RRAM）的系统和方法
公开(公告)号：WO2014062558A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064811
申请日：2013-10-14
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
IPC分类号： G11C11/16 , G11C13/00 , G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/1653 , G11C11/1673 , G11C11/1693 , G11C13/0002 , G11C13/0061
摘要： A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell.
摘要翻译：一种包括连接到字线和位线的电阻性随机存取存储器单元的系统，以及配置成将该位线预充电到第一电压而未被选择的预充电电路。驱动器电路在位线被充电到第一电压之后的第一时间选择字线。比较器将位线上的第二电压与提供给比较器的第三电压进行比较，并根据比较产生输出。锁存器锁存比较器的输出并产生锁存输出。脉冲发生器在第一次之后的延迟之后产生脉冲以对时钟锁存器锁存比较器的输出并产生锁存的输出。锁存的输出表示电阻随机存取存储单元的状态。

36. 发明申请

WO2014062554A1 APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS 审中-公开
标题翻译：用于修复电阻记忆体的装置和方法，并增加感知放大器的整体读出灵敏度
公开(公告)号：WO2014062554A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064801
申请日：2013-10-14
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
IPC分类号： G11C29/02
CPC分类号： G11C7/065 , G11C7/06 , G11C7/067 , G11C7/1057 , G11C7/106 , G11C11/1653 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C29/026
摘要： A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch.
摘要翻译：存储器包括模块和解复用器。该模块配置为监视读出放大器的输出。读出放大器的每个输出被配置为处于第一状态或第二状态。该模块被配置为确定读出放大器的两个或多个输出处于相同状态。同样的状态是第一个状态或第二个状态。该模块被配置为输出读出放大器的两个或多个输出的状态。解复用器被配置为将读出放大器的两个或更多个输出的状态提供给锁存器。

37. 发明申请

WO2013078311A1 FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION 审中-公开
标题翻译：用于快速响应和减少功率的变速系统的频率调整
公开(公告)号：WO2013078311A1
公开(公告)日：2013-05-30
申请号：PCT/US2012/066257
申请日：2012-11-21
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , SUTARDJA, Sehat
发明人： SUTARDJA, Pantas , SUTARDJA, Sehat
IPC分类号： G06F1/08 , G06F1/32 , H03L7/00
CPC分类号： H03K3/02 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
摘要翻译：一种包括配置成产生具有频率的时钟信号的多个放大器的系统。时钟信号被输入到处理器。放大器串联。最后一个放大器的输出被反馈到第一个放大器的输入端。每个放大器都有跨导。频率调整模块被配置为通过调节放大器的跨导来调整基于处理器的活动电平的时钟信号的频率。

38. 发明申请

WO2013028632A1 REGULATOR FOR LED LIGHTING COLOR MIXING 审中-公开
标题翻译： LED照明颜色混合调节器
公开(公告)号：WO2013028632A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/051610
申请日：2012-08-20
申请人： MARVELL SEMICONDUCTOR, INC. , SUTARDJA, Sehat , SUTARDJA, Pantas , ZHANG, Wanfeng
发明人： SUTARDJA, Sehat , SUTARDJA, Pantas , ZHANG, Wanfeng
IPC分类号： H05B33/08
CPC分类号： H05B33/0815 , H05B33/0857 , Y02B20/347
摘要： A system includes a first light emitting diode configured to produce light of a first color and a second light emitting diode configured to produce light of a second color. A constant current circuit is configured to provide a first current, wherein (i) the first current is approximately constant, (ii) a first portion of the first current flows through the second light emitting diode, and (iii) a remaining portion of the first current flows through the first light emitting diode. A current regulating circuit is configured to control the first portion of the first current flowing through the second light emitting diode. The current regulating circuit is connected in series with the second light emitting diode, the constant current circuit, and a reference potential. The first light emitting diode is connected in series directly between the constant current circuit and the reference potential.
摘要翻译：一种系统包括被配置为产生第一颜色的光的第一发光二极管和被配置为产生第二颜色的光的第二发光二极管。恒流电路被配置为提供第一电流，其中（i）第一电流近似恒定，（ii）第一电流的第一部分流过第二发光二极管，以及（iii）剩余部分第一电流流过第一发光二极管。电流调节电路被配置为控制流过第二发光二极管的第一电流的第一部分。电流调节电路与第二发光二极管，恒流电路和参考电位串联。第一个发光二极管直接连接在恒流电路和参考电位之间。

39. 发明申请

WO2011137442A1 SYSTEM AND METHOD OF TUNING CURRENT FOR LEDS 审中-公开
标题翻译： LED电流调节系统及方法
公开(公告)号：WO2011137442A1
公开(公告)日：2011-11-03
申请号：PCT/US2011/034799
申请日：2011-05-02
申请人： MARVELL WORLD TRADE LTD , ZHANG, Wanfeng , SUTARDJA, Pantas
发明人： ZHANG, Wanfeng , SUTARDJA, Pantas
IPC分类号： H05B33/08
CPC分类号： H05B33/0845 , H05B33/086 , H05B37/0263
摘要： An apparatus includes a LED and a regulator circuit. The regulator circuit controls the current provided to the LED according to a calibration signal that is coupled to the current. The regulator circuit adjusts the output of the LED when the calibration signal is adjusted. In this manner, the LED may be calibrated to generate light at a desired brightness level and color level.
摘要翻译：一种装置包括LED和调节器电路。调节器电路根据耦合到电流的校准信号控制提供给LED的电流。当调节校准信号时，调节器电路调节LED的输出。以这种方式，可以校准LED以产生期望的亮度级和色彩级的光。

40. 发明申请

WO2009100108A1 SYSTEM AND METHOD FOR DECODING A MEMORY ARRAY COMPRISING BLOCKS AND SUB-BLOCKS 审中-公开
标题翻译：用于解码包含块和子块的存储器阵列的系统和方法
公开(公告)号：WO2009100108A1
公开(公告)日：2009-08-13
申请号：PCT/US2009/033040
申请日：2009-02-04
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , LEE, Winston
发明人： SUTARDJA, Pantas , LEE, Winston
IPC分类号： G11C8/14 , G11C7/18 , G11C7/10
CPC分类号： G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C8/14 , G11C2207/2209
摘要： A memory system includes Q memory blocks (216) that each include M memory sub-blocks (224). The memory system also includes Q word line decoders (206) that each are associated with a different one of the Q memory blocks (216). The memory system also includes a bit line decoder (309) and Q x M switch modules (319). Each Q x M switch module selectively controls access to one of the M memory sub-blocks of the Q memory blocks. The Q word line decoders and the bit line decoder access less than M memory sub-blocks in at least two of the Q memory blocks during one of a read and write operation. M and Q are integers greater than 1.
摘要翻译：存储器系统包括Q存储器块（216），每个存储器块包括M个存储器子块（224）。存储器系统还包括Q字线解码器（206），每个Q字线解码器都与Q存储器块（216）中的不同的一个相关联。存储器系统还包括位线解码器（309）和Q×M开关模块（319）。每个Q x M开关模块选择性地控制对Q存储器块的M个存储器子块之一的访问。在读取和写入操作期间，Q字线解码器和位线解码器在至少两个Q存储器块中访问少于M个存储器子块。 M和Q是大于1的整数。

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