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31. 发明授权

US5238530A Anisotropic titanate etch 失效
标题翻译：各向异性钛酸盐蚀刻
公开(公告)号：US5238530A
公开(公告)日：1993-08-24
申请号：US871863
申请日：1992-04-20
申请人： Monte A. Douglas , Howard R. Beratan , Scott R. Summerfelt
发明人： Monte A. Douglas , Howard R. Beratan , Scott R. Summerfelt
IPC分类号： C04B41/53 , C04B41/91 , H01L21/02 , H01L21/311
CPC分类号： H01L28/55 , C04B41/5353 , C04B41/91 , H01L21/31111
摘要： A titanate substrate (e.g. lead zirconate titanate 34) is immersed in a liquid ambient (e.g. 12 molar concentration hydrochloric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the titanate substrate 34. An etch mask 32 may be positioned between the radiation source 20 and the substrate 34. The titanate substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the titanate is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.
摘要翻译：将钛酸酯基材（例如锆钛酸铅34）浸入液体环境（例如12摩尔浓度的盐酸30）中，并用辐射源（例如200瓦汞氙）产生的辐射（例如准直的可见/紫外线辐射24）照射弧光灯20）。对准直辐射24基本上透明的窗口26允许辐射能量到达钛酸盐衬底34.蚀刻掩模32可以位于辐射源20和衬底34之间。钛酸盐衬底34和液态环境30被保持在标称温度（例如25℃）下。在没有照明的情况下，钛酸盐不被液体环境明显腐蚀。在照射时，蚀刻速率显着增加。

32. 发明授权

US5201989A Anisotropic niobium pentoxide etch 失效
标题翻译：各向异性五氧化二铌蚀刻
公开(公告)号：US5201989A
公开(公告)日：1993-04-13
申请号：US872701
申请日：1992-04-20
申请人： Monte A. Douglas , Howard R. Beratan , Scott R. Summerfelt
发明人： Monte A. Douglas , Howard R. Beratan , Scott R. Summerfelt
IPC分类号： B01J19/12 , C01G33/00 , C04B41/53 , C04B41/91 , C23F1/04 , C23F1/30 , H01L21/02 , H01L21/311
CPC分类号： C04B41/009 , C04B41/5353 , C04B41/91 , H01L21/31111 , H01L28/40 , C04B2111/00387 , H01L28/55
摘要： A niobium pentoxide substrate 34 immersed in a liquid ambient (e.g. 10% hydrofluoric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the Nb.sub.2 O.sub.5 substrate 34. An etch mask (e.g. organic photoresist 32) may be positioned between the radiation source 20 and the substrate 34. The Nb.sub.2 O.sub.5 substrate 34 and liquid ambient 30 are maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the Nb.sub.2 O.sub.5 is not appreciably etched by the liquid ambient. Upon illumination the etch rate is substantially increased.
摘要翻译：浸渍在液体环境（例如10％氢氟酸30）中并用辐射源（例如，200瓦汞氙弧灯20）产生的辐射（例如准直的可见/紫外线辐射24）照射的五氧化二铌衬底34。对准直辐射24基本透明的窗口26允许辐射能量到达Nb 2 O 5衬底34.蚀刻掩模（例如有机光致抗蚀剂32）可以位于辐射源20和衬底34之间.Nb 2 O 5衬底34和液体环境30保持在标称温度（例如25℃）。在没有照明的情况下，Nb 2 O 5不被液体环境明显腐蚀。在照射时，蚀刻速率显着增加。

33. 发明授权

US08658474B2 Contact and via interconnects using metal around dielectric pillars 有权
标题翻译：使用金属周围介质柱的接触和通孔互连
公开(公告)号：US08658474B2
公开(公告)日：2014-02-25
申请号：US13050581
申请日：2011-03-17
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： H01L21/82
CPC分类号： H01L21/76885 , H01L21/76877 , H01L23/5226 , H01L23/5227 , H01L23/5286 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
摘要翻译：一种包含垂直互连的集成电路，其包括连续围绕一个或多个介电柱的互连金属区域。垂直互连电接触下导电结构的顶表面。上导电结构接触垂直互连的顶表面。形成集成电路的过程包括形成具有连续围绕一个或多个介电柱的互连金属区域的垂直互连。垂直互连电接触下导电结构的顶表面，并且上导电结构接触垂直互连的顶表面。

34. 发明授权

US08441833B2 Differential plate line screen test for ferroelectric latch circuits 有权
标题翻译：铁电锁存电路的差分板线屏蔽测试
公开(公告)号：US08441833B2
公开(公告)日：2013-05-14
申请号：US13445076
申请日：2012-04-12
申请人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
发明人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译：构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。单独的板线连接到互补存储节点的铁电电容器。通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。

35. 发明授权

US08380476B2 Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties 有权
标题翻译：铁电电容器的建模包括铁电性质的局部统计变化
公开(公告)号：US08380476B2
公开(公告)日：2013-02-19
申请号：US12568910
申请日：2009-09-29
申请人： Borna Obradovic , Keith R. Green , Scott R. Summerfelt
发明人： Borna Obradovic , Keith R. Green , Scott R. Summerfelt
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036
摘要： Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the superposed polarization of each of the randomly selected domains.
摘要翻译：包括铁电电容器型号的电子电路仿真。铁电电容器的模型包括多畴铁电电容器，其中每个畴与正矫顽电压和负矫顽电压相关联。定义正矫顽电压和负矫顽电压的概率分布函数，从而确定具有矫顽电压的域的分布的加权函数。为了创建小型铁电电容器的模型，将Poisson概率分布分配给定义正和负矫顽电压的概率分布函数的网格单元阵列中的每一个，并且分配给每个网格单元的域的数量根据该格子随机选择基于建模电容器的面积，该网格单元的建模电容器的泊松分布和预期数量的域。通过评估每个随机选择的畴的叠加极化来评估铁电电容器的电性能。

36. 发明授权

US08377719B2 Drawn dummy FeCAP, via and metal structures 有权
标题翻译：绘制虚拟FeCAP，通孔和金属结构
公开(公告)号：US08377719B2
公开(公告)日：2013-02-19
申请号：US13307829
申请日：2011-11-30
申请人： Scott R. Summerfelt , Rajni J. Aggarwal
发明人： Scott R. Summerfelt , Rajni J. Aggarwal
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/585 , H01L27/0207 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.
摘要翻译：形成集成电路的过程，该集成电路包含具有相同布局的匹配部件和在匹配部件上具有相同构造的氢可渗透虚设通孔。

37. 发明申请

US20120195096A1 DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS 有权
标题翻译：用于电磁绞线电路的差分线路屏蔽测试
公开(公告)号：US20120195096A1
公开(公告)日：2012-08-02
申请号：US13445076
申请日：2012-04-12
申请人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
发明人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译：构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。单独的板线连接到互补存储节点的铁电电容器。通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。

38. 发明申请

US20120077287A1 DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES 有权
标题翻译：抽烟费，通风和金属结构
公开(公告)号：US20120077287A1
公开(公告)日：2012-03-29
申请号：US13307829
申请日：2011-11-30
申请人： Scott R. Summerfelt , Rajni J. Aggarwal
发明人： Scott R. Summerfelt , Rajni J. Aggarwal
IPC分类号： H01L21/02
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/585 , H01L27/0207 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/00
摘要： A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.
摘要翻译：形成集成电路的过程，该集成电路包含具有相同布局的匹配部件和在匹配部件上具有相同构造的氢可渗透虚设通孔。

39. 发明申请

US20120070993A1 PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS 有权
标题翻译：含有电解电容器和氢气障碍物的集成电路的钝化
公开(公告)号：US20120070993A1
公开(公告)日：2012-03-22
申请号：US13303541
申请日：2011-11-23
申请人： Scott R. Summerfelt , Ted S. Moise , Gul B. Basim
发明人： Scott R. Summerfelt , Ted S. Moise , Gul B. Basim
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , H01L21/0217 , H01L21/76832 , H01L21/76834 , H01L23/5223 , H01L27/11509 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.
摘要翻译：一种用于形成覆盖铁电电容器和缓冲区域但是从逻辑区域的一部分去除的氢阻挡层的方法。

40. 发明授权

US08058677B2 Stress buffer layer for ferroelectric random access memory 有权
公开(公告)号：US08058677B2
公开(公告)日：2011-11-15
申请号：US12396976
申请日：2009-03-03
申请人： Scott R. Summerfelt , Kezhakkedath R. Udayakumar , John P. Campbell , Hugh P. McAdams
发明人： Scott R. Summerfelt , Kezhakkedath R. Udayakumar , John P. Campbell , Hugh P. McAdams
IPC分类号： H01L23/28
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

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