专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20080034236A1 Method and program for generating execution code for performing parallel processing 有权
标题翻译：用于生成用于执行并行处理的执行代码的方法和程序
公开(公告)号：US20080034236A1
公开(公告)日：2008-02-07
申请号：US11707146
申请日：2007-02-16
申请人： Koichi Takayama , Naonobu Sukegawa
发明人： Koichi Takayama , Naonobu Sukegawa
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F8/4432 , Y02D10/41
摘要： Provided is a method of reliably reducing power consumption of a computer, while promoting prompt compilation of a source code and execution of an output code. The method according to this invention includes the steps of: reading a code which is preset and analyzing an amount of operation of the CPU and an access amount with respect to the cache memory based on the code; obtaining an execution rate of the CPU and an access rate with respect to the cache memory based on the amount of operation and the access amount; determining an area in which the access rate with respect to the cache memory is higher than the execution rate of the CPU, based on the code; adding a code for enabling the power consumption reduction function to the area; and generating an execution code executable on the computer, based on the code.
摘要翻译：提供了一种可靠地降低计算机的功耗的方法，同时促进对源代码的及时编译和输出代码的执行。根据本发明的方法包括以下步骤：基于代码读取预设的代码和分析CPU的操作量和关于高速缓冲存储器的访问量; 基于操作量和访问量，获得CPU的执行率和相对于高速缓冲存储器的访问速率; 基于代码，确定相对于高速缓冲存储器的访问速率高于CPU的执行速率的区域; 为该区域增加一个能够实现功耗降低功能的代码; 以及基于所述代码在所述计算机上生成可执行的执行代码。

32. 发明申请

US20070180198A1 Processor for multiprocessing computer systems and a computer system 审中-公开
标题翻译：用于多处理计算机系统和计算机系统的处理器
公开(公告)号：US20070180198A1
公开(公告)日：2007-08-02
申请号：US11358052
申请日：2006-02-22
申请人： Hidetaka Aoki , Naonobu Sukegawa
发明人： Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/6028
摘要： When the same data is used in a multiprocessor system, cache misses are reduced to prevent a coherence request from frequently occurring between processors. Provided is a processor including: an interface for performing communication with a main memory or one of the another processor through a system control unit; a cache memory for storing data of the main memory; and a reading processing unit for reading data at an address contained in a reading instruction from the main memory to store the read data in the cache memory, in which the reading processing unit includes: a first load instruction executing unit for reading data corresponding to an address designated by a first load instruction from the main memory and the one of the another processor to store the data into the cache memory; and a second load instruction executing unit for reading data corresponding to an address designated by a second load instruction from the main memory or the one of the another processor to store the data into the cache memory and requesting the system control unit to transmit the data to the another processor
摘要翻译：当在多处理器系统中使用相同的数据时，减少高速缓存未命中，以防止在处理器之间频繁发生相干请求。提供了一种处理器，包括：用于通过系统控制单元执行与主存储器或另一处理器之一的通信的接口; 用于存储主存储器的数据的高速缓冲存储器; 以及读取处理单元，用于从包含在来自主存储器的读取指令中的地址读取数据，以将读取的数据存储在高速缓冲存储器中，读取处理单元包括：第一加载指令执行单元，用于读取对应于由来自主存储器的第一加载指令指定的地址和另一个处理器之一，将数据存储到高速缓冲存储器中; 以及第二加载指令执行单元，用于从主存储器或另一处理器中的一个处理器读取与由第二加载指令指定的地址相对应的数据，以将数据存储到高速缓冲存储器中，并请求系统控制单元将数据发送到另一个处理器

33. 发明申请

US20070124567A1 Processor system 审中-公开
标题翻译：处理器系统
公开(公告)号：US20070124567A1
公开(公告)日：2007-05-31
申请号：US11357972
申请日：2006-02-22
申请人： Aki Tomita , Hidetaka Aoki , Naonobu Sukegawa
发明人： Aki Tomita , Hidetaka Aoki , Naonobu Sukegawa
IPC分类号： G06F15/00
CPC分类号： G06F15/167
摘要： A processor system capable of improving usability and performance of an on-chip heterogeneous multiprocessor is provided. The processor system has a processor and a memory, the processor including one control unit that reads a program, a plurality of arithmetic units that transmit a SIMD instruction of the program read by the control unit, and a shared cache capable of storing the program read by the control unit from the memory and allowing the control unit and the plurality of arithmetic units to read and write data. An instruction transmitted from the control unit to the plurality of arithmetic units specifies, in a process where the plurality of arithmetic units execute instructions, whether, until receiving an external signal from an arithmetic unit different from the arithmetic unit that is executing the instruction, execution of the instruction is to be suspended.
摘要翻译：提供了一种能够提高片上异构多处理器的可用性和性能的处理器系统。处理器系统具有处理器和存储器，处理器包括读取程序的一个控制单元，发送由控制单元读取的程序的SIMD指令的多个运算单元，以及能够存储程序读取的共享高速缓存并且允许控制单元和多个运算单元读取和写入数据。从所述控制单元发送到所述多个算术单元的指令，在所述多个算术单元执行指令的处理中，在从与所述指令执行的运算单元不同的运算单元接收到外部信号之前，的指示将被暂停。

34. 发明授权

US5778429A Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas 失效
标题翻译：并行处理器系统包括具有可独立寻址的本地和远程数据区的高速缓存存储器子系统
公开(公告)号：US5778429A
公开(公告)日：1998-07-07
申请号：US497751
申请日：1995-07-03
申请人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
发明人： Naonobu Sukegawa , Tshiaki Tarui , Hiroaki Fujii , Hideya Akashi
IPC分类号： G06F15/17 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0848 , G06F2212/272
摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.
摘要翻译：并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式